FPGA dynamic power minimization through placement and routing constraints. Wang, L., French, M., Davoodi, A., & Agarwal, D. EURASIP J. Embedded Syst., 2006:7–7, Hindawi Publishing Corp., New York, NY, United States, January, 2006. ![FPGA dynamic power minimization through placement and routing constraints [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi bibtex @article{Wang:2006:FDP:1288223.1288230,
author = {Wang, Li and French, Matthew and Davoodi, Azadeh and Agarwal, Deepak},
title = {FPGA dynamic power minimization through placement and routing constraints},
journal = {EURASIP J. Embedded Syst.},
issue_date = {January 2006},
volume = {2006},
issue = {1},
month = {January},
year = {2006},
issn = {1687-3955},
pages = {7--7},
numpages = {1},
url = {http://dx.doi.org/10.1155/ES/2006/31605},
doi = {http://dx.doi.org/10.1155/ES/2006/31605},
acmid = {1288230},
publisher = {Hindawi Publishing Corp.},
address = {New York, NY, United States},
}
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