A Fault Tolerant, Area Efficient Architecture for Shor's Factoring Algorithm. Whitney, M. G., Isailovic, N., Patel, Y., & Kubiatowicz, J. In Proceedings of the 36th Annual International Symposium on Computer Architecture, of ISCA '09, pages 383–394, New York, NY, USA, 2009. ACM. ZSCC: 0000046 event-place: Austin, TX, USA![A Fault Tolerant, Area Efficient Architecture for Shor's Factoring Algorithm [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi abstract bibtex We optimize the area and latency of Shor's factoring while simultaneously improving fault tolerance through: (1) balancing the use of ancilla generators, (2) aggressive optimization of error correction, and (3) tuning the core adder circuits. Our custom CAD flow produces detailed layouts of the physical components and utilizes simulation to analyze circuits in terms of area, latency, and success probability. We introduce a metric, called ADCR, which is the probabilistic equivalent of the classic Area-Delay product. Our error correction optimization can reduce ADCR by order of magnitude or more. Contrary to conventional wisdom, we show that the area of an optimized quantum circuit is not dominated exclusively by error correction. Further, our adder evaluation shows that quantum carry-lookahead adders (QCLA) beat ripple-carry adders in ADCR, despite being larger and more complex. We conclude with what we believe is one of most accurate estimates of the area and latency required for 1024-bit Shor's factorization: 7659 mm2 for the smallest circuit and 6 x 108 seconds for the fastest circuit.
@inproceedings{whitney_fault_2009,
address = {New York, NY, USA},
series = {{ISCA} '09},
title = {A {Fault} {Tolerant}, {Area} {Efficient} {Architecture} for {Shor}'s {Factoring} {Algorithm}},
isbn = {978-1-60558-526-0},
url = {http://doi.acm.org/10.1145/1555754.1555802},
doi = {10/dh4s42},
abstract = {We optimize the area and latency of Shor's factoring while simultaneously improving fault tolerance through: (1) balancing the use of ancilla generators, (2) aggressive optimization of error correction, and (3) tuning the core adder circuits. Our custom CAD flow produces detailed layouts of the physical components and utilizes simulation to analyze circuits in terms of area, latency, and success probability. We introduce a metric, called ADCR, which is the probabilistic equivalent of the classic Area-Delay product. Our error correction optimization can reduce ADCR by order of magnitude or more. Contrary to conventional wisdom, we show that the area of an optimized quantum circuit is not dominated exclusively by error correction. Further, our adder evaluation shows that quantum carry-lookahead adders (QCLA) beat ripple-carry adders in ADCR, despite being larger and more complex. We conclude with what we believe is one of most accurate estimates of the area and latency required for 1024-bit Shor's factorization: 7659 mm2 for the smallest circuit and 6 x 108 seconds for the fastest circuit.},
urldate = {2019-11-05},
booktitle = {Proceedings of the 36th {Annual} {International} {Symposium} on {Computer} {Architecture}},
publisher = {ACM},
author = {Whitney, Mark G. and Isailovic, Nemanja and Patel, Yatish and Kubiatowicz, John},
year = {2009},
note = {ZSCC: 0000046
event-place: Austin, TX, USA},
keywords = {cad, control, ion trap, layout, quantum computing},
pages = {383--394}
}
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