A Survey on Assertion-based Hardware Verification. Witharana, H., Lyu, Y., Charles, S., & Mishra, P. ACM Computing Surveys, January, 2022.
A Survey on Assertion-based Hardware Verification [link]Paper  doi  abstract   bibtex   
Hardware veriication of modern electronic systems has been identiied as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware veriication is to drastically reduce the validation and debug time without sacriicing the design quality. Assertion-based veriication is a promising avenue for eicient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware veriication. Speciically, we outline how to deine assertions using temporal logic to specify expected behaviors in diferent abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements. CCS Concepts: · Hardware → Functional veriication; Assertion checking; Post-manufacture validation and debug; Bug detection, localization and diagnosis.
@article{witharana_survey_2022,
	title = {A {Survey} on {Assertion}-based {Hardware} {Verification}},
	issn = {0360-0300, 1557-7341},
	url = {https://dl.acm.org/doi/10.1145/3510578},
	doi = {10.1145/3510578},
	abstract = {Hardware veriication of modern electronic systems has been identiied as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware veriication is to drastically reduce the validation and debug time without sacriicing the design quality. Assertion-based veriication is a promising avenue for eicient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware veriication. Speciically, we outline how to deine assertions using temporal logic to specify expected behaviors in diferent abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements. CCS Concepts: · Hardware → Functional veriication; Assertion checking; Post-manufacture validation and debug; Bug detection, localization and diagnosis.},
	language = {en},
	urldate = {2022-08-19},
	journal = {ACM Computing Surveys},
	author = {Witharana, Hasini and Lyu, Yangdi and Charles, Subodha and Mishra, Prabhat},
	month = jan,
	year = {2022},
	pages = {3510578},
}

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