A Survey on Assertion-based Hardware Verification. Witharana, H., Lyu, Y., Charles, S., & Mishra, P. ACM Computing Surveys, January, 2022. ![A Survey on Assertion-based Hardware Verification [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi abstract bibtex Hardware veriication of modern electronic systems has been identiied as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware veriication is to drastically reduce the validation and debug time without sacriicing the design quality. Assertion-based veriication is a promising avenue for eicient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware veriication. Speciically, we outline how to deine assertions using temporal logic to specify expected behaviors in diferent abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements. CCS Concepts: · Hardware → Functional veriication; Assertion checking; Post-manufacture validation and debug; Bug detection, localization and diagnosis.
@article{witharana_survey_2022,
title = {A {Survey} on {Assertion}-based {Hardware} {Verification}},
issn = {0360-0300, 1557-7341},
url = {https://dl.acm.org/doi/10.1145/3510578},
doi = {10.1145/3510578},
abstract = {Hardware veriication of modern electronic systems has been identiied as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware veriication is to drastically reduce the validation and debug time without sacriicing the design quality. Assertion-based veriication is a promising avenue for eicient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware veriication. Speciically, we outline how to deine assertions using temporal logic to specify expected behaviors in diferent abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements. CCS Concepts: · Hardware → Functional veriication; Assertion checking; Post-manufacture validation and debug; Bug detection, localization and diagnosis.},
language = {en},
urldate = {2022-08-19},
journal = {ACM Computing Surveys},
author = {Witharana, Hasini and Lyu, Yangdi and Charles, Subodha and Mishra, Prabhat},
month = jan,
year = {2022},
pages = {3510578},
}
Downloads: 0
{"_id":"W6bqADjGMKgSYcDzu","bibbaseid":"witharana-lyu-charles-mishra-asurveyonassertionbasedhardwareverification-2022","author_short":["Witharana, H.","Lyu, Y.","Charles, S.","Mishra, P."],"bibdata":{"bibtype":"article","type":"article","title":"A Survey on Assertion-based Hardware Verification","issn":"0360-0300, 1557-7341","url":"https://dl.acm.org/doi/10.1145/3510578","doi":"10.1145/3510578","abstract":"Hardware veriication of modern electronic systems has been identiied as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware veriication is to drastically reduce the validation and debug time without sacriicing the design quality. Assertion-based veriication is a promising avenue for eicient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware veriication. Speciically, we outline how to deine assertions using temporal logic to specify expected behaviors in diferent abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements. CCS Concepts: · Hardware → Functional veriication; Assertion checking; Post-manufacture validation and debug; Bug detection, localization and diagnosis.","language":"en","urldate":"2022-08-19","journal":"ACM Computing Surveys","author":[{"propositions":[],"lastnames":["Witharana"],"firstnames":["Hasini"],"suffixes":[]},{"propositions":[],"lastnames":["Lyu"],"firstnames":["Yangdi"],"suffixes":[]},{"propositions":[],"lastnames":["Charles"],"firstnames":["Subodha"],"suffixes":[]},{"propositions":[],"lastnames":["Mishra"],"firstnames":["Prabhat"],"suffixes":[]}],"month":"January","year":"2022","pages":"3510578","bibtex":"@article{witharana_survey_2022,\n\ttitle = {A {Survey} on {Assertion}-based {Hardware} {Verification}},\n\tissn = {0360-0300, 1557-7341},\n\turl = {https://dl.acm.org/doi/10.1145/3510578},\n\tdoi = {10.1145/3510578},\n\tabstract = {Hardware veriication of modern electronic systems has been identiied as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware veriication is to drastically reduce the validation and debug time without sacriicing the design quality. Assertion-based veriication is a promising avenue for eicient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware veriication. Speciically, we outline how to deine assertions using temporal logic to specify expected behaviors in diferent abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements. CCS Concepts: · Hardware → Functional veriication; Assertion checking; Post-manufacture validation and debug; Bug detection, localization and diagnosis.},\n\tlanguage = {en},\n\turldate = {2022-08-19},\n\tjournal = {ACM Computing Surveys},\n\tauthor = {Witharana, Hasini and Lyu, Yangdi and Charles, Subodha and Mishra, Prabhat},\n\tmonth = jan,\n\tyear = {2022},\n\tpages = {3510578},\n}\n\n","author_short":["Witharana, H.","Lyu, Y.","Charles, S.","Mishra, P."],"key":"witharana_survey_2022","id":"witharana_survey_2022","bibbaseid":"witharana-lyu-charles-mishra-asurveyonassertionbasedhardwareverification-2022","role":"author","urls":{"Paper":"https://dl.acm.org/doi/10.1145/3510578"},"metadata":{"authorlinks":{}},"downloads":0,"html":""},"bibtype":"article","biburl":"https://bibbase.org/zotero/bxt101","dataSources":["Wsv2bQ4jPuc7qme8R"],"keywords":[],"search_terms":["survey","assertion","based","hardware","verification","witharana","lyu","charles","mishra"],"title":"A Survey on Assertion-based Hardware Verification","year":2022}