Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling

Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling. Xu, X., Luo, Q., Gong, T., Lv, H., Long, S., Liu, Q., Chung, S. S., Li, J., & Liu, M. In 2016 IEEE Symposium on VLSI Technology, pages 1–2, June, 2016.
doi bibtex

@INPROCEEDINGS{xu2016vlsi, 
author={Xiaoxin Xu and Q. Luo and Tiancheng Gong and Hangbing Lv and Shibing Long and Qi Liu and S. S. Chung and Jing Li and Ming Liu}, 
booktitle={2016 IEEE Symposium on VLSI Technology}, 
title={Fully {CMOS} compatible {3D} vertical {RRAM} with self-aligned self-selective cell enabling sub-5nm scaling}, 
year={2016}, 
date={2016-06},
volume={}, 
number={}, 
pages={1--2}, 
keywords={conference, CMOS memory circuits,integrated circuit manufacture,resistive RAM,CMOS,RRAM,self-aligned self-selective cell,size 5 nm,vertical resistive switching memory,Etching,Hafnium compounds,Leakage currents,Programming,Resistance,Three-dimensional displays,Threshold voltage}, 
doi={10.1109/VLSIT.2016.7573388}, 
ISSN={}, 
month={June},}

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