A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform Traffic Arbitration at Routing Logic. Yadav, S., Laxmi, V., & Gaur, M. S. In 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016, pages 69–74, 2016.
A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform Traffic Arbitration at Routing Logic [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/vlsid/YadavLG16,
  author       = {Sonal Yadav and
                  Vijay Laxmi and
                  Manoj Singh Gaur},
  title        = {A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform
                  Traffic Arbitration at Routing Logic},
  booktitle    = {29th International Conference on {VLSI} Design and 15th International
                  Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
                  4-8, 2016},
  pages        = {69--74},
  year         = {2016},
  crossref     = {DBLP:conf/vlsid/2016},
  url          = {https://doi.org/10.1109/VLSID.2016.104},
  doi          = {10.1109/VLSID.2016.104},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/YadavLG16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

Downloads: 0