@inproceedings{conf/vdat/YadavLGB15,
  added-at = {2015-08-27T00:00:00.000+0200},
  author = {Yadav, Sonal and Laxmi, Vijay and Gaur, Manoj Singh and Bhargava, Megha},
  biburl = {http://www.bibsonomy.org/bibtex/24c7252947b08041075924ed671791a57/dblp},
  booktitle = {VDAT},
  crossref = {conf/vdat/2015},
  ee = {http://dx.doi.org/10.1109/ISVDAT.2015.7208068},
  interhash = {ef72ee7614a0ea24b0858797ddf482ed},
  intrahash = {4c7252947b08041075924ed671791a57},
  isbn = {978-1-4799-1743-3},
  keywords = {dblp},
  pages = {1-2},
  publisher = {IEEE},
  timestamp = {2015-08-29T11:37:38.000+0200},
  title = {C2-DLM: Cache coherence aware dual link mesh for on-chip interconnect.},
  url = {http://dblp.uni-trier.de/db/conf/vdat/vdat2015.html#YadavLGB15},
  year = 2015
}

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