C\(^\mbox2\)-DLM: Cache coherence aware dual link mesh for on-chip interconnect. Yadav, S., Laxmi, V., Gaur, M. S., & Bhargava, M. In 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015, pages 1–2, 2015.
C\(^\mbox2\)-DLM: Cache coherence aware dual link mesh for on-chip interconnect [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/vdat/YadavLGB15,
  author    = {Sonal Yadav and
               Vijay Laxmi and
               Manoj Singh Gaur and
               Megha Bhargava},
  title     = {C\({}^{\mbox{2}}\)-DLM: Cache coherence aware dual link mesh for on-chip
               interconnect},
  booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
               Ahmedabad, India, June 26-29, 2015},
  pages     = {1--2},
  year      = {2015},
  crossref  = {DBLP:conf/vdat/2015},
  url       = {https://doi.org/10.1109/ISVDAT.2015.7208068},
  doi       = {10.1109/ISVDAT.2015.7208068},
  timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vdat/YadavLGB15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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