Optimizing power and performance for reliable on-chip networks. Yanamandra, A., Eachempati, S., Soundararajan, N., Narayanan, V., Irwin, M. J., & Krishnan, R. In ASP-DAC, pages 431-436, 2010. IEEE.
Optimizing power and performance for reliable on-chip networks. [link]Link  Optimizing power and performance for reliable on-chip networks. [link]Paper  bibtex   
@inproceedings{conf/aspdac/YanamandraESNIK10,
  added-at = {2016-05-20T00:00:00.000+0200},
  author = {Yanamandra, Aditya and Eachempati, Soumya and Soundararajan, Niranjan and Narayanan, Vijaykrishnan and Irwin, Mary Jane and Krishnan, Ramakrishnan},
  biburl = {http://www.bibsonomy.org/bibtex/27b187a1c46220772d1463c03d5eb4705/dblp},
  booktitle = {ASP-DAC},
  crossref = {conf/aspdac/2010},
  ee = {http://dl.acm.org/citation.cfm?id=1899826},
  interhash = {723f6251f48bcce337924567f1a21bc3},
  intrahash = {7b187a1c46220772d1463c03d5eb4705},
  isbn = {978-1-60558-837-7},
  keywords = {dblp},
  pages = {431-436},
  publisher = {IEEE},
  timestamp = {2016-05-21T12:31:39.000+0200},
  title = {Optimizing power and performance for reliable on-chip networks.},
  url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#YanamandraESNIK10},
  year = 2010
}

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