On-Chip Traffic Regulation to Reduce Coherence Protocol Cost on a Micro-threaded Many-Core Architecture with Distributed Caches. Yang, Q., Fu, J., Poss, R., & Jesshope, C. ACM Trans. Embed. Comput. Syst., 13(3s):103:1–103:21, ACM, New York, NY, USA, March, 2013. ![On-Chip Traffic Regulation to Reduce Coherence Protocol Cost on a Micro-threaded Many-Core Architecture with Distributed Caches [link]](https://bibbase.org/img/filetypes/link.svg "link")
Doi doi abstract bibtex When hardware cache coherence scales to many cores on chip, the coherence protocol of the shared memory system may offset the benefit from massive hardware concurrency. In this article, we investigate the cost of a write-update policy in terms of on-chip memory network traffic and its adverse effects on the system performance based on a multi-threaded many-core architecture with distributed caches. We discuss possible software and hardware solutions to alleviate the network pressure without changing the protocol. We find that in the context of massive concurrency, by introducing a write-merging buffer with 0.46% area overhead to each core, applications with good locality and concurrency are boosted up by 18.74% in performance on average. Other applications also benefit from this addition and even achieve a throughput increase of 5.93%. In addition, this improvement indicates that higher levels of concurrency per core can be exploited without impacting performance, thus tolerating latency better and giving higher processor efficiencies compared to other solutions.
@article{yang13tecs,
Abstract = {When hardware cache coherence scales to many cores on chip, the coherence protocol of the shared memory system may offset the benefit from massive hardware concurrency. In this article, we investigate the cost of a write-update policy in terms of on-chip memory network traffic and its adverse effects on the system performance based on a multi-threaded many-core architecture with distributed caches. We discuss possible software and hardware solutions to alleviate the network pressure without changing the protocol. We find that in the context of massive concurrency, by introducing a write-merging buffer with 0.46% area overhead to each core, applications with good locality and concurrency are boosted up by 18.74% in performance on average. Other applications also benefit from this addition and even achieve a throughput increase of 5.93%. In addition, this improvement indicates that higher levels of concurrency per core can be exploited without impacting performance, thus tolerating latency better and giving higher processor efficiencies compared to other solutions.},
Acmid = {2567931},
Address = {New York, NY, USA},
Author = {Qiang Yang and Jian Fu and Raphael Poss and Chris Jesshope},
Doi = {10.1145/2567931}, Urldoi = {http://dx.doi.org/10.1145/2567931},
Issn = {1539-9087},
Journal = {ACM Trans. Embed. Comput. Syst.},
Month = {March},
Number = {3s},
Pages = {103:1--103:21},
Publisher = {ACM},
Title = {On-Chip Traffic Regulation to Reduce Coherence Protocol Cost on a Micro-threaded Many-Core Architecture with Distributed Caches},
Volume = {13},
Year = {2013},
}
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{"_id":{"_str":"5342bd570e946d920a003505"},"__v":1,"authorIDs":["54c2dea9b5fb1e5511000919","5dfafc26fa2bbbde01000122","5e35eb445cd57fde01000070","5e38ff13dc5b8ade01000077","5e64a5962551dede01000063","ZGRaLkjmxPcmJ739z","efnDKftzuGYiXXauW","pgjx6rQxQDmzHuwRK","sCob7zjTXbp95CmbP"],"author_short":["Yang, Q.","Fu, J.","Poss, R.","Jesshope, C."],"bibbaseid":"yang-fu-poss-jesshope-onchiptrafficregulationtoreducecoherenceprotocolcostonamicrothreadedmanycorearchitecturewithdistributedcaches-2013","bibdata":{"bibtype":"article","type":"article","abstract":"When hardware cache coherence scales to many cores on chip, the coherence protocol of the shared memory system may offset the benefit from massive hardware concurrency. In this article, we investigate the cost of a write-update policy in terms of on-chip memory network traffic and its adverse effects on the system performance based on a multi-threaded many-core architecture with distributed caches. We discuss possible software and hardware solutions to alleviate the network pressure without changing the protocol. We find that in the context of massive concurrency, by introducing a write-merging buffer with 0.46% area overhead to each core, applications with good locality and concurrency are boosted up by 18.74% in performance on average. Other applications also benefit from this addition and even achieve a throughput increase of 5.93%. In addition, this improvement indicates that higher levels of concurrency per core can be exploited without impacting performance, thus tolerating latency better and giving higher processor efficiencies compared to other solutions.","acmid":"2567931","address":"New York, NY, USA","author":[{"firstnames":["Qiang"],"propositions":[],"lastnames":["Yang"],"suffixes":[]},{"firstnames":["Jian"],"propositions":[],"lastnames":["Fu"],"suffixes":[]},{"firstnames":["Raphael"],"propositions":[],"lastnames":["Poss"],"suffixes":[]},{"firstnames":["Chris"],"propositions":[],"lastnames":["Jesshope"],"suffixes":[]}],"doi":"10.1145/2567931","urldoi":"http://dx.doi.org/10.1145/2567931","issn":"1539-9087","journal":"ACM Trans. Embed. Comput. Syst.","month":"March","number":"3s","pages":"103:1–103:21","publisher":"ACM","title":"On-Chip Traffic Regulation to Reduce Coherence Protocol Cost on a Micro-threaded Many-Core Architecture with Distributed Caches","volume":"13","year":"2013","bibtex":"@article{yang13tecs,\n\tAbstract = {When hardware cache coherence scales to many cores on chip, the coherence protocol of the shared memory system may offset the benefit from massive hardware concurrency. In this article, we investigate the cost of a write-update policy in terms of on-chip memory network traffic and its adverse effects on the system performance based on a multi-threaded many-core architecture with distributed caches. We discuss possible software and hardware solutions to alleviate the network pressure without changing the protocol. We find that in the context of massive concurrency, by introducing a write-merging buffer with 0.46% area overhead to each core, applications with good locality and concurrency are boosted up by 18.74% in performance on average. Other applications also benefit from this addition and even achieve a throughput increase of 5.93%. In addition, this improvement indicates that higher levels of concurrency per core can be exploited without impacting performance, thus tolerating latency better and giving higher processor efficiencies compared to other solutions.},\n\tAcmid = {2567931},\n\tAddress = {New York, NY, USA},\n\tAuthor = {Qiang Yang and Jian Fu and Raphael Poss and Chris Jesshope},\n\n\n\tDoi = {10.1145/2567931}, Urldoi = {http://dx.doi.org/10.1145/2567931},\n\tIssn = {1539-9087},\n\tJournal = {ACM Trans. Embed. Comput. Syst.},\n\tMonth = {March},\n\tNumber = {3s},\n\tPages = {103:1--103:21},\n\tPublisher = {ACM},\n\tTitle = {On-Chip Traffic Regulation to Reduce Coherence Protocol Cost on a Micro-threaded Many-Core Architecture with Distributed Caches},\n\tVolume = {13},\n\tYear = {2013},\n\t}\n\n","author_short":["Yang, Q.","Fu, J.","Poss, R.","Jesshope, C."],"key":"yang13tecs","id":"yang13tecs","bibbaseid":"yang-fu-poss-jesshope-onchiptrafficregulationtoreducecoherenceprotocolcostonamicrothreadedmanycorearchitecturewithdistributedcaches-2013","role":"author","urls":{"Doi":"http://dx.doi.org/10.1145/2567931"},"metadata":{"authorlinks":{"poss, r":"https://bibbase.org/show?bib=https%3A%2F%2Fscience.raphael.poss.name%2Fpub.bib"}},"downloads":0,"html":""},"bibtype":"article","biburl":"science.raphael.poss.name/pub.bib","downloads":0,"keywords":[],"search_terms":["chip","traffic","regulation","reduce","coherence","protocol","cost","micro","threaded","many","core","architecture","distributed","caches","yang","fu","poss","jesshope"],"title":"On-Chip Traffic Regulation to Reduce Coherence Protocol Cost on a Micro-threaded Many-Core Architecture with Distributed Caches","year":2013,"dataSources":["75cdFjzQkYc9cKbYS","nMjrEFThibKqpZt4n","ob9Lo6tki9nBzzxK9"]}