Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. Yang, Y., Huang, Q., Wu, B., Zhang, T., Ma, L., Gambardella, G., Blott, M., Lavagno, L., Vissers, K. A., Wawrzynek, J., & Keutzer, K. CoRR, 2018.
Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. [link]Link  Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. [link]Paper  bibtex   
@article{journals/corr/abs-1811-08634,
  added-at = {2020-06-18T00:00:00.000+0200},
  author = {Yang, Yifan and Huang, Qijing and Wu, Bichen and Zhang, Tianjun and Ma, Liang and Gambardella, Giulio and Blott, Michaela and Lavagno, Luciano and Vissers, Kees A. and Wawrzynek, John and Keutzer, Kurt},
  biburl = {https://www.bibsonomy.org/bibtex/2ad869a643bc137535b211513e4c20c13/dblp},
  ee = {http://arxiv.org/abs/1811.08634},
  interhash = {6d8551f83d22f2d4afe62c641b681506},
  intrahash = {ad869a643bc137535b211513e4c20c13},
  journal = {CoRR},
  keywords = {dblp},
  timestamp = {2020-06-19T11:39:01.000+0200},
  title = {Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.},
  url = {http://dblp.uni-trier.de/db/journals/corr/corr1811.html#abs-1811-08634},
  volume = {abs/1811.08634},
  year = 2018
}
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