@inproceedings{conf/fpga/YangHWZ0GBLVWK19,
  added-at = {2020-06-18T00:00:00.000+0200},
  author = {Yang, Yifan and Huang, Qijing and Wu, Bichen and Zhang, Tianjun and Ma, Liang and Gambardella, Giulio and Blott, Michaela and Lavagno, Luciano and Vissers, Kees A. and Wawrzynek, John and Keutzer, Kurt},
  biburl = {https://www.bibsonomy.org/bibtex/23f5c8b223598e7842657beed4640b6f4/dblp},
  booktitle = {FPGA},
  crossref = {conf/fpga/2019},
  editor = {Bazargan, Kia and Neuendorffer, Stephen},
  ee = {https://doi.org/10.1145/3289602.3293902},
  interhash = {d93210e16e975fd93bc05990fea35c39},
  intrahash = {3f5c8b223598e7842657beed4640b6f4},
  isbn = {978-1-4503-6137-8},
  keywords = {dblp},
  pages = {23-32},
  publisher = {ACM},
  timestamp = {2020-06-19T11:43:00.000+0200},
  title = {Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.},
  url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2019.html#YangHWZ0GBLVWK19},
  year = 2019
}

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