@article{journals/tvlsi/YangM18,
  added-at = {2018-08-11T00:00:00.000+0200},
  author = {Yang, Ping-Lin and Marek-Sadowska, Malgorzata},
  biburl = {https://www.bibsonomy.org/bibtex/2aff9db0af5660b835f3aebd6cf701c30/dblp},
  ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2814627},
  interhash = {ed23986f7cfa95441305c958644d577a},
  intrahash = {aff9db0af5660b835f3aebd6cf701c30},
  journal = {IEEE Trans. VLSI Syst.},
  keywords = {dblp},
  number = 7,
  pages = {1209-1222},
  timestamp = {2018-08-14T11:38:22.000+0200},
  title = {High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators.},
  url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#YangM18},
  volume = 26,
  year = 2018
}

{"_id":"PTabMe4J7QHdxiyQF","bibbaseid":"yang-mareksadowska-highperformancearchitectureusingfastdynamicreconfigurableaccelerators-2018","authorIDs":[],"author_short":["Yang, P.","Marek-Sadowska, M."],"bibdata":{"bibtype":"article","type":"article","added-at":"2018-08-11T00:00:00.000+0200","author":[{"propositions":[],"lastnames":["Yang"],"firstnames":["Ping-Lin"],"suffixes":[]},{"propositions":[],"lastnames":["Marek-Sadowska"],"firstnames":["Malgorzata"],"suffixes":[]}],"biburl":"https://www.bibsonomy.org/bibtex/2aff9db0af5660b835f3aebd6cf701c30/dblp","ee":"http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2814627","interhash":"ed23986f7cfa95441305c958644d577a","intrahash":"aff9db0af5660b835f3aebd6cf701c30","journal":"IEEE Trans. VLSI Syst.","keywords":"dblp","number":"7","pages":"1209-1222","timestamp":"2018-08-14T11:38:22.000+0200","title":"High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators.","url":"http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#YangM18","volume":"26","year":"2018","bibtex":"@article{journals/tvlsi/YangM18,\n added-at = {2018-08-11T00:00:00.000+0200},\n author = {Yang, Ping-Lin and Marek-Sadowska, Malgorzata},\n biburl = {https://www.bibsonomy.org/bibtex/2aff9db0af5660b835f3aebd6cf701c30/dblp},\n ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2814627},\n interhash = {ed23986f7cfa95441305c958644d577a},\n intrahash = {aff9db0af5660b835f3aebd6cf701c30},\n journal = {IEEE Trans. VLSI Syst.},\n keywords = {dblp},\n number = 7,\n pages = {1209-1222},\n timestamp = {2018-08-14T11:38:22.000+0200},\n title = {High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators.},\n url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#YangM18},\n volume = 26,\n year = 2018\n}\n\n","author_short":["Yang, P.","Marek-Sadowska, M."],"key":"journals/tvlsi/YangM18","id":"journals/tvlsi/YangM18","bibbaseid":"yang-mareksadowska-highperformancearchitectureusingfastdynamicreconfigurableaccelerators-2018","role":"author","urls":{"Link":"http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2814627","Paper":"http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#YangM18"},"keyword":["dblp"],"downloads":0},"bibtype":"article","biburl":"http://www.bibsonomy.org/bib/author/yang lin?items=1000","creationDate":"2019-08-22T03:53:53.741Z","downloads":0,"keywords":["dblp"],"search_terms":["high","performance","architecture","using","fast","dynamic","reconfigurable","accelerators","yang","marek-sadowska"],"title":"High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators.","year":2018,"dataSources":["a57oXwvfTysj8WtNo"]}