High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. Yang, P. & Marek-Sadowska, M. IEEE Trans. VLSI Syst., 26(7):1209-1222, 2018.
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. [link]Link  High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. [link]Paper  bibtex   
@article{journals/tvlsi/YangM18,
  added-at = {2018-08-11T00:00:00.000+0200},
  author = {Yang, Ping-Lin and Marek-Sadowska, Malgorzata},
  biburl = {https://www.bibsonomy.org/bibtex/2aff9db0af5660b835f3aebd6cf701c30/dblp},
  ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2814627},
  interhash = {ed23986f7cfa95441305c958644d577a},
  intrahash = {aff9db0af5660b835f3aebd6cf701c30},
  journal = {IEEE Trans. VLSI Syst.},
  keywords = {dblp},
  number = 7,
  pages = {1209-1222},
  timestamp = {2018-08-14T11:38:22.000+0200},
  title = {High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators.},
  url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#YangM18},
  volume = 26,
  year = 2018
}
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