Secure Scan: A Design-for-Test Architecture for Crypto Chips. Yang, B., Wu, K., & Karri, R. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(10):2287-2293, 10, 2006.
Secure Scan: A Design-for-Test Architecture for Crypto Chips [link]Website  bibtex   
@article{
 title = {Secure Scan: A Design-for-Test Architecture for Crypto Chips},
 type = {article},
 year = {2006},
 identifiers = {[object Object]},
 pages = {2287-2293},
 volume = {25},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=1677712},
 month = {10},
 id = {eba15687-4fac-33d2-8787-0ef9e82f6910},
 created = {2016-04-07T10:34:34.000Z},
 accessed = {2016-03-30},
 file_attached = {false},
 profile_id = {f1db73c3-239d-36d4-8bb0-bab363f5c6ac},
 group_id = {43f2be07-c028-3da9-a55e-4f12e16d4053},
 last_modified = {2016-04-07T10:34:34.000Z},
 read = {false},
 starred = {false},
 authored = {false},
 confirmed = {false},
 hidden = {false},
 bibtype = {article},
 author = {Yang, B. and Wu, K. and Karri, R.},
 journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
 number = {10}
}

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