What to Lock?: Functional and Parametric Locking

What to Lock?: Functional and Parametric Locking. Yasin, M., Sengupta, A., Schafer, B. C., Makris, Y., Sinanoglu, O., & Rajendran, J. (. In Proceedings of the on Great Lakes Symposium on VLSI 2017 - GLSVLSI '17, pages 351–356, Banff, Alberta, Canada, 2017. ACM Press.

Paper doi abstract bibtex

Logic locking is an intellectual property (IP) protection technique that prevents IP piracy, reverse engineering and overbuilding attacks by the untrusted foundry or end-users. Existing logic locking techniques are all based on locking the functionality; the design/chip is nonfunctional unless the secret key has been loaded. Existing techniques are vulnerable to various attacks, such as sensitization, key-pruning, and signal skew analysis enabled removal attacks. In this paper, we propose a tenacious and traceless logic locking technique, TTlock, that locks functionality and provably withstands all known attacks, such as SAT-based, sensitization, removal, etc. TTLock protects a secret input pattern; the output of a logic cone is ﬂipped for that pattern, where this ﬂip is restored only when the correct key is applied. Experimental results conﬁrm our theoretical expectations that the computational complexity of attacks launched on TTLock grows exponentially with increasing key-size, while the area, power, and delay overhead increases only linearly. In this paper, we also coin “parametric locking,” where the design/chip behaves as per its speciﬁcations (performance, power, reliability, etc.) only with the secret key in place, and an incorrect key downgrades its parametric characteristics. We discuss objectives and challenges in parametric locking.

@inproceedings{yasin_what_2017,
	address = {Banff, Alberta, Canada},
	title = {What to {Lock}?: {Functional} and {Parametric} {Locking}},
	isbn = {978-1-4503-4972-7},
	shorttitle = {What to {Lock}?},
	url = {http://dl.acm.org/citation.cfm?doid=3060403.3060492},
	doi = {10.1145/3060403.3060492},
	abstract = {Logic locking is an intellectual property (IP) protection technique that prevents IP piracy, reverse engineering and overbuilding attacks by the untrusted foundry or end-users. Existing logic locking techniques are all based on locking the functionality; the design/chip is nonfunctional unless the secret key has been loaded. Existing techniques are vulnerable to various attacks, such as sensitization, key-pruning, and signal skew analysis enabled removal attacks. In this paper, we propose a tenacious and traceless logic locking technique, TTlock, that locks functionality and provably withstands all known attacks, such as SAT-based, sensitization, removal, etc. TTLock protects a secret input pattern; the output of a logic cone is ﬂipped for that pattern, where this ﬂip is restored only when the correct key is applied. Experimental results conﬁrm our theoretical expectations that the computational complexity of attacks launched on TTLock grows exponentially with increasing key-size, while the area, power, and delay overhead increases only linearly. In this paper, we also coin “parametric locking,” where the design/chip behaves as per its speciﬁcations (performance, power, reliability, etc.) only with the secret key in place, and an incorrect key downgrades its parametric characteristics. We discuss objectives and challenges in parametric locking.},
	language = {en},
	urldate = {2020-03-17},
	booktitle = {Proceedings of the on {Great} {Lakes} {Symposium} on {VLSI} 2017 - {GLSVLSI} '17},
	publisher = {ACM Press},
	author = {Yasin, Muhammad and Sengupta, Abhrajit and Schafer, Benjamin Carrion and Makris, Yiorgos and Sinanoglu, Ozgur and Rajendran, Jeyavijayan (JV)},
	year = {2017},
	keywords = {\#broken, boolean satisfiability, ip piracy, logic encryption, logic locking, reverse engineering},
	pages = {351--356},
}

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{"_id":"CiDZ8yNqdhAmjqLx5","bibbaseid":"yasin-sengupta-schafer-makris-sinanoglu-rajendran-whattolockfunctionalandparametriclocking-2017","author_short":["Yasin, M.","Sengupta, A.","Schafer, B. C.","Makris, Y.","Sinanoglu, O.","Rajendran, J. (."],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","address":"Banff, Alberta, Canada","title":"What to Lock?: Functional and Parametric Locking","isbn":"978-1-4503-4972-7","shorttitle":"What to Lock?","url":"http://dl.acm.org/citation.cfm?doid=3060403.3060492","doi":"10.1145/3060403.3060492","abstract":"Logic locking is an intellectual property (IP) protection technique that prevents IP piracy, reverse engineering and overbuilding attacks by the untrusted foundry or end-users. Existing logic locking techniques are all based on locking the functionality; the design/chip is nonfunctional unless the secret key has been loaded. Existing techniques are vulnerable to various attacks, such as sensitization, key-pruning, and signal skew analysis enabled removal attacks. In this paper, we propose a tenacious and traceless logic locking technique, TTlock, that locks functionality and provably withstands all known attacks, such as SAT-based, sensitization, removal, etc. TTLock protects a secret input pattern; the output of a logic cone is ﬂipped for that pattern, where this ﬂip is restored only when the correct key is applied. Experimental results conﬁrm our theoretical expectations that the computational complexity of attacks launched on TTLock grows exponentially with increasing key-size, while the area, power, and delay overhead increases only linearly. In this paper, we also coin “parametric locking,” where the design/chip behaves as per its speciﬁcations (performance, power, reliability, etc.) only with the secret key in place, and an incorrect key downgrades its parametric characteristics. We discuss objectives and challenges in parametric locking.","language":"en","urldate":"2020-03-17","booktitle":"Proceedings of the on Great Lakes Symposium on VLSI 2017 - GLSVLSI '17","publisher":"ACM Press","author":[{"propositions":[],"lastnames":["Yasin"],"firstnames":["Muhammad"],"suffixes":[]},{"propositions":[],"lastnames":["Sengupta"],"firstnames":["Abhrajit"],"suffixes":[]},{"propositions":[],"lastnames":["Schafer"],"firstnames":["Benjamin","Carrion"],"suffixes":[]},{"propositions":[],"lastnames":["Makris"],"firstnames":["Yiorgos"],"suffixes":[]},{"propositions":[],"lastnames":["Sinanoglu"],"firstnames":["Ozgur"],"suffixes":[]},{"propositions":[],"lastnames":["Rajendran"],"firstnames":["Jeyavijayan","(JV)"],"suffixes":[]}],"year":"2017","keywords":"#broken, boolean satisfiability, ip piracy, logic encryption, logic locking, reverse engineering","pages":"351–356","bibtex":"@inproceedings{yasin_what_2017,\n\taddress = {Banff, Alberta, Canada},\n\ttitle = {What to {Lock}?: {Functional} and {Parametric} {Locking}},\n\tisbn = {978-1-4503-4972-7},\n\tshorttitle = {What to {Lock}?},\n\turl = {http://dl.acm.org/citation.cfm?doid=3060403.3060492},\n\tdoi = {10.1145/3060403.3060492},\n\tabstract = {Logic locking is an intellectual property (IP) protection technique that prevents IP piracy, reverse engineering and overbuilding attacks by the untrusted foundry or end-users. Existing logic locking techniques are all based on locking the functionality; the design/chip is nonfunctional unless the secret key has been loaded. Existing techniques are vulnerable to various attacks, such as sensitization, key-pruning, and signal skew analysis enabled removal attacks. In this paper, we propose a tenacious and traceless logic locking technique, TTlock, that locks functionality and provably withstands all known attacks, such as SAT-based, sensitization, removal, etc. TTLock protects a secret input pattern; the output of a logic cone is ﬂipped for that pattern, where this ﬂip is restored only when the correct key is applied. Experimental results conﬁrm our theoretical expectations that the computational complexity of attacks launched on TTLock grows exponentially with increasing key-size, while the area, power, and delay overhead increases only linearly. In this paper, we also coin “parametric locking,” where the design/chip behaves as per its speciﬁcations (performance, power, reliability, etc.) only with the secret key in place, and an incorrect key downgrades its parametric characteristics. We discuss objectives and challenges in parametric locking.},\n\tlanguage = {en},\n\turldate = {2020-03-17},\n\tbooktitle = {Proceedings of the on {Great} {Lakes} {Symposium} on {VLSI} 2017 - {GLSVLSI} '17},\n\tpublisher = {ACM Press},\n\tauthor = {Yasin, Muhammad and Sengupta, Abhrajit and Schafer, Benjamin Carrion and Makris, Yiorgos and Sinanoglu, Ozgur and Rajendran, Jeyavijayan (JV)},\n\tyear = {2017},\n\tkeywords = {\\#broken, boolean satisfiability, ip piracy, logic encryption, logic locking, reverse engineering},\n\tpages = {351--356},\n}\n\n\n\n","author_short":["Yasin, M.","Sengupta, A.","Schafer, B. C.","Makris, Y.","Sinanoglu, O.","Rajendran, J. (."],"key":"yasin_what_2017","id":"yasin_what_2017","bibbaseid":"yasin-sengupta-schafer-makris-sinanoglu-rajendran-whattolockfunctionalandparametriclocking-2017","role":"author","urls":{"Paper":"http://dl.acm.org/citation.cfm?doid=3060403.3060492"},"keyword":["#broken","boolean satisfiability","ip piracy","logic encryption","logic locking","reverse engineering"],"metadata":{"authorlinks":{}},"html":""},"bibtype":"inproceedings","biburl":"https://bibbase.org/zotero/bxt101","dataSources":["Wsv2bQ4jPuc7qme8R"],"keywords":["#broken","boolean satisfiability","ip piracy","logic encryption","logic locking","reverse engineering"],"search_terms":["lock","functional","parametric","locking","yasin","sengupta","schafer","makris","sinanoglu","rajendran"],"title":"What to Lock?: Functional and Parametric Locking","year":2017}