@article{DBLP:journals/tcad/YehCHYH14,
  author    = {Sheng{-}Han Yeh and
               Jia{-}Wen Chang and
               Tsung{-}Wei Huang and
               Shang{-}Tsung Yu and
               Tsung{-}Yi Ho},
  title     = {Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained
               {EWOD} Chips},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {33},
  number    = {9},
  pages     = {1302--1315},
  year      = {2014},
  url       = {https://doi.org/10.1109/TCAD.2014.2331340},
  doi       = {10.1109/TCAD.2014.2331340},
  timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/YehCHYH14},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

{"_id":"nkS6ZEwowXksvPgDg","bibbaseid":"yeh-chang-huang-yu-ho-voltageawarechipleveldesignforreliabilitydrivenpinconstrainedewodchips-2014","authorIDs":[],"author_short":["Yeh, S.","Chang, J.","Huang, T.","Yu, S.","Ho, T."],"bibdata":{"bibtype":"article","type":"article","author":[{"firstnames":["Sheng-Han"],"propositions":[],"lastnames":["Yeh"],"suffixes":[]},{"firstnames":["Jia-Wen"],"propositions":[],"lastnames":["Chang"],"suffixes":[]},{"firstnames":["Tsung-Wei"],"propositions":[],"lastnames":["Huang"],"suffixes":[]},{"firstnames":["Shang-Tsung"],"propositions":[],"lastnames":["Yu"],"suffixes":[]},{"firstnames":["Tsung-Yi"],"propositions":[],"lastnames":["Ho"],"suffixes":[]}],"title":"Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips","journal":"IEEE Trans. on CAD of Integrated Circuits and Systems","volume":"33","number":"9","pages":"1302–1315","year":"2014","url":"https://doi.org/10.1109/TCAD.2014.2331340","doi":"10.1109/TCAD.2014.2331340","timestamp":"Wed, 25 Sep 2019 01:00:00 +0200","biburl":"https://dblp.org/rec/bib/journals/tcad/YehCHYH14","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@article{DBLP:journals/tcad/YehCHYH14,\n author = {Sheng{-}Han Yeh and\n Jia{-}Wen Chang and\n Tsung{-}Wei Huang and\n Shang{-}Tsung Yu and\n Tsung{-}Yi Ho},\n title = {Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained\n {EWOD} Chips},\n journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},\n volume = {33},\n number = {9},\n pages = {1302--1315},\n year = {2014},\n url = {https://doi.org/10.1109/TCAD.2014.2331340},\n doi = {10.1109/TCAD.2014.2331340},\n timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},\n biburl = {https://dblp.org/rec/bib/journals/tcad/YehCHYH14},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Yeh, S.","Chang, J.","Huang, T.","Yu, S.","Ho, T."],"key":"DBLP:journals/tcad/YehCHYH14","id":"DBLP:journals/tcad/YehCHYH14","bibbaseid":"yeh-chang-huang-yu-ho-voltageawarechipleveldesignforreliabilitydrivenpinconstrainedewodchips-2014","role":"author","urls":{"Paper":"https://doi.org/10.1109/TCAD.2014.2331340"},"downloads":0,"html":""},"bibtype":"article","biburl":"https://ycunxi.github.io/utah-csl/bibtex/all.bib","creationDate":"2019-11-14T21:37:03.812Z","downloads":0,"keywords":[],"search_terms":["voltage","aware","chip","level","design","reliability","driven","pin","constrained","ewod","chips","yeh","chang","huang","yu","ho"],"title":"Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips","year":2014,"dataSources":["L6BLFSB28hKk5Nt67"]}