A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. Yoshimoto, S., Miyano, S., Takamiya, M., Shinohara, H., Kawaguchi, H., & Yoshimoto, M. In CICC, pages 1-4, 2013. IEEE.
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. [link]Link  A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. [link]Paper  bibtex   
@inproceedings{conf/cicc/YoshimotoMTSKY13,
  added-at = {2024-03-11T00:00:00.000+0100},
  author = {Yoshimoto, Shusuke and Miyano, Shinji and Takamiya, Makoto and Shinohara, Hirofumi and Kawaguchi, Hiroshi and Yoshimoto, Masahiko},
  biburl = {https://www.bibsonomy.org/bibtex/2374fcaefbc698d964bcdfa974f4dd5fa/dblp},
  booktitle = {CICC},
  crossref = {conf/cicc/2013},
  ee = {https://doi.org/10.1109/CICC.2013.6658537},
  interhash = {89c6680332be6fbc4550bf03cab30171},
  intrahash = {374fcaefbc698d964bcdfa974f4dd5fa},
  keywords = {dblp},
  pages = {1-4},
  publisher = {IEEE},
  timestamp = {2024-04-10T22:11:07.000+0200},
  title = {A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure.},
  url = {http://dblp.uni-trier.de/db/conf/cicc/cicc2013.html#YoshimotoMTSKY13},
  year = 2013
}

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