@inproceedings{conf/aspdac/YoshimotoTOSMKY13,
  added-at = {2024-03-11T00:00:00.000+0100},
  author = {Yoshimoto, Shusuke and Terada, Masaharu and Okumura, Shunsuke and Suzuki, Toshikazu and Miyano, Shinji and Kawaguchi, Hiroshi and Yoshimoto, Masahiko},
  biburl = {https://www.bibsonomy.org/bibtex/238dad9bb1e81f98dc5d5c3c1f919ce0e/dblp},
  booktitle = {ASP-DAC},
  crossref = {conf/aspdac/2013},
  ee = {https://doi.org/10.1109/ASPDAC.2013.6509564},
  interhash = {9f8a2a75233862133542eeb36ddad8e1},
  intrahash = {38dad9bb1e81f98dc5d5c3c1f919ce0e},
  isbn = {978-1-4673-3029-9},
  keywords = {dblp},
  pages = {77-78},
  publisher = {IEEE},
  timestamp = {2024-04-10T04:16:21.000+0200},
  title = {A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique.},
  url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2013.html#YoshimotoTOSMKY13},
  year = 2013
}

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