Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering. Yu, C. & Ciesielski, M. J. IEEE Trans. on CAD of Integrated Circuits and Systems, 38(2):354–365, 2019.
Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering [link]Paper  doi  bibtex   
@article{DBLP:journals/tcad/YuC19,
  author    = {Cunxi Yu and
               Maciej J. Ciesielski},
  title     = {Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification
               and Reverse Engineering},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {38},
  number    = {2},
  pages     = {354--365},
  year      = {2019},
  url       = {https://doi.org/10.1109/TCAD.2018.2808457},
  doi       = {10.1109/TCAD.2018.2808457},
  timestamp = {Wed, 13 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/YuC19},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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