A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. Yun, W., Lee, H., Shin, D., Kang, S., Yang, J., Lee, H., Lee, D., Sim, S., Kim 0001, Y., Choi, W., Song, K., Shin, S., Choi, H., Moon, H., Kwack, S., Lee, J., Choi, Y., Park, N., Kim, K., Choi, Y., Ahn, J., & Seok Yang, Y. In Proceedings of International Solid-State Circuits Conference (ISSCC), pages 282-283, 2008.
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology [link]Paper  bibtex   
@inproceedings{ dblp3400513,
  title = {A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology},
  author = {Won-Joo Yun and Hyun-Woo Lee and Dongsuk Shin and Shin-Deok Kang and Ji-Yeon Yang and Hyeng-Ouk Lee and Dong-Uk Lee and Sujeong Sim and Young-Ju Kim 0001 and Won-Jun Choi and Keun-Soo Song and Sang-Hoon Shin and Hyang-Hwa Choi and Hyung-Wook Moon and Seung-Wook Kwack and Jung-Woo Lee and Young-Kyoung Choi and Nak-Kyu Park and Kwan-Weon Kim and Young-Jung Choi and Jin-Hong Ahn and Ye Seok Yang},
  author_short = {Yun, W. and Lee, H. and Shin, D. and Kang, S. and Yang, J. and Lee, H. and Lee, D. and Sim, S. and Kim 0001, Y. and Choi, W. and Song, K. and Shin, S. and Choi, H. and Moon, H. and Kwack, S. and Lee, J. and Choi, Y. and Park, N. and Kim, K. and Choi, Y. and Ahn, J. and Seok Yang, Y.},
  bibtype = {inproceedings},
  type = {inproceedings},
  year = {2008},
  key = {dblp3400513},
  id = {dblp3400513},
  biburl = {http://www.dblp.org/rec/bibtex/conf/isscc/YunLSKYLLSKCSSCMKLCPKCAY08},
  url = {http://dx.doi.org/10.1109/ISSCC.2008.4523167},
  conference = {ISSCC},
  pages = {282-283},
  text = {ISSCC 2008:282-283},
  booktitle = {Proceedings of International Solid-State Circuits Conference (ISSCC)}
}

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