@article{
 title = {A 1.8 v tri-mode ∑Δ modulator for GSM/WCDMA/WLAN wireless receiver},
 type = {article},
 year = {2006},
 identifiers = {[object Object]},
 keywords = {Multi-standard,Sigma-Delta modulator,Wireless receiver},
 volume = {49},
 id = {d41b4e87-e1aa-3308-a572-4e881199005b},
 created = {2017-12-04T05:34:57.428Z},
 file_attached = {false},
 profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
 last_modified = {2017-12-04T05:34:57.428Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {The next generation of cellular systems will be increasingly similar to a data communication system. Not only will it transfer voice and multimedia data, it will also be integrated with WLAN to access Internet whenever possible. Thus these cellular systems need highly integrated multi-standard receivers. The design of the A/D converter in such receivers is a big challenge. A GSM/WCDMA/WLAN tri-mode receiver is first designed on the system level. A reconfigurable ∑Δ modulator, which is suitable for GSM/WCDMA/WLAN receiver, is then proposed in this paper. According to the different signal bandwidth and Dynamic Range (DR) specifications, this ∑Δ modulator is reconfigured to achieve the required dynamic range with less power consumption. The prototype is implemented in TSMC 0.18-μm CMOS process with 1.8 V power supply. The circuit achieves signal-to-noise-and-distortion-ratio of 82 dB for GSM, 75 dB for WCDMA and 58.dB for WLAN. © Springer Science + Business Media, LLC 2006.},
 bibtype = {article},
 author = {Zhang, L. and Kim, H.J. and Nadig, V. and Ismail, M.},
 journal = {Analog Integrated Circuits and Signal Processing},
 number = {3}
}

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