Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling. Zhang, S., Li, X., Blanton, R. D., da Silva, Machado, J., Jr., Carulli, J. M., & Butler, K. M. In ITC, pages 1-10, 2014. IEEE Computer Society. Link Paper bibtex @inproceedings{ conf/itc/ZhangLBSCB14,
added-at = {2015-08-26T00:00:00.000+0200},
author = {Zhang, Shanghang and Li, Xin and Blanton, Ronald D. and da Silva, José Machado and Jr., John M. Carulli and Butler, Kenneth M.},
biburl = {http://www.bibsonomy.org/bibtex/2f60f79d1b91aaf5a79d7c8475145d1b7/dblp},
booktitle = {ITC},
crossref = {conf/itc/2014},
ee = {http://doi.ieeecomputersociety.org/10.1109/TEST.2014.7035328},
interhash = {2f99023a16aafe0164c6134d9690f230},
intrahash = {f60f79d1b91aaf5a79d7c8475145d1b7},
isbn = {978-1-4799-4722-5},
keywords = {dblp},
pages = {1-10},
publisher = {IEEE Computer Society},
title = {Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.},
url = {http://dblp.uni-trier.de/db/conf/itc/itc2014.html#ZhangLBSCB14},
year = {2014}
}
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