RRAM-based reconfigurable in-memory computing architecture with hybrid routing

RRAM-based reconfigurable in-memory computing architecture with hybrid routing. Zha<sup>S</sup>, Y. & Li, J. In 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), of <strong>ICCAD</strong> '17, pages 527–532, Nov, 2017. (Acceptance Rate: 26%, 105 out of 399)
doi abstract bibtex

Recent advances in resistive random-access memory (RRAM) evoke great interests in exploring alternative architectures. One interesting work is a RRAM-based reconfigurable architecture that provides superior programmbility and blurs the boundary between computation and storage, but long-distance routing becomes a performance bottleneck. However, long-distance routing in FPGA is efficiently implemented, but its fine-grained routing structure results in a large routing overhead. In this work, we present a RRAM-based reconfigurable architecture that addresses the routing challenges using hybrid routing, i.e., local and global routing by taking the best advantages of both architectures (prior RRAM-based and FPGA). We also provide a complete CAD framework that exhibits high parallelism and good scalability. Experimental results show that our reconfigurable architecture outperforms both architectures. It achieves a 46.88% reduction in delay and improves the energy efficiency by 66.23% compared with the prior RRAM-based architecture with a slightly increased area overhead. While comparing with FPGA, it reduces the delay and the routing overhead by 36.00% and 50.20%, respectively. Additionally, our CAD framework achieves 5.39x speedup, compared with the prior framework.

@INPROCEEDINGS{zha2017iccad, 
author={Yue Zha<sup>S</sup> and Jing Li}, 
booktitle={2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}, 
series = {<strong>ICCAD</strong> '17},
title={{RRAM-based} reconfigurable in-memory computing architecture with hybrid routing}, 
year={2017}, 
month={Nov},
date={2017-11-13},
volume={}, 
number={}, 
pages={527--532}, 
keywords={conference, Architecture,Delays,Field programmable gate arrays,Logic functions,Routing,Switches,Tiles,CAD Framework,Hybrid Routing,In-Memory Computing,Reconfigurable Architecture,liquid Silicon}, 
abstract={Recent advances in resistive random-access memory (RRAM) evoke great interests in exploring alternative architectures. One interesting work is a RRAM-based reconfigurable architecture that provides superior programmbility and blurs the boundary between computation and storage, but long-distance routing becomes a performance bottleneck. However, long-distance routing in FPGA is efficiently implemented, but its fine-grained routing structure results in a large routing overhead. In this work, we present a RRAM-based reconfigurable architecture that addresses the routing challenges using hybrid routing, i.e., local and global routing by taking the best advantages of both architectures (prior RRAM-based and FPGA). We also provide a complete CAD framework that exhibits high parallelism and good scalability. Experimental results show that our reconfigurable architecture outperforms both architectures. It achieves a 46.88\% reduction in delay and improves the energy efficiency by 66.23\% compared with the prior RRAM-based architecture with a slightly increased area overhead. While comparing with FPGA, it reduces the delay and the routing overhead by 36.00\% and 50.20\%, respectively. Additionally, our CAD framework achieves 5.39x speedup, compared with the prior framework.},
doi={10.1109/ICCAD.2017.8203822}, 
ISSN={1558-2434}, 
note = {(Acceptance Rate: <u>26\%</u>, 105 out of 399)},
}

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