A Mixed-Signal Data-Centric Reconfigurable Architecture Enabled by RRAM Technology (poster)

A Mixed-Signal Data-Centric Reconfigurable Architecture Enabled by RRAM Technology (poster). ZhaS, Y., ZhangS, J., Wei, Z., & Li, J. In Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, of FPGA '17, pages 285–285, New York, NY, USA, 2017. ACM.

Paper doi bibtex

@inproceedings{zha2017FPGAposter,
 author = {Zha<sup>S</sup>, Yue and Zhang<sup>S</sup>, Jialiang and Wei, Zhiqiang and Li, Jing},
 title = {A Mixed-Signal Data-Centric Reconfigurable Architecture Enabled by {RRAM} Technology (poster)},
 booktitle = {Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
 series = {<strong>FPGA</strong> '17},
 year = {2017},
 date={2017-02-22},
 isbn = {978-1-4503-4354-1},
 location = {Monterey, California, USA},
 pages = {285--285},
 numpages = {1},
 url = {http://doi.acm.org/10.1145/3020078.3021759},
 doi = {10.1145/3020078.3021759},
 acmid = {3021759},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {conference, coarse-grained configuration, mixed-signal processing, non-volatile memory, reconfigurable architecture, ternary content addressable memory},
% note = {(Acceptance Rate: <u>25\%</u>, 25 out of 101)},
}

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