Verification of timed circuits with failure-directed abstractions. Zheng, H., Myers, C. J., Walter, D., Little, S., & Yoneda, T. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(3):403–412, 2006. Paper doi bibtex @article{DBLP:journals/tcad/ZhengMWLY06,
author = {Hao Zheng and
Chris J. Myers and
David Walter and
Scott Little and
Tomohiro Yoneda},
title = {Verification of timed circuits with failure-directed abstractions},
journal = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
volume = {25},
number = {3},
pages = {403--412},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.854638},
doi = {10.1109/TCAD.2005.854638},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/bib/journals/tcad/ZhengMWLY06},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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