@inproceedings{
 title = {Analytical performance estimation from GSMP model for hierarchical bus-bridge based SoC communication architecture},
 type = {inproceedings},
 year = {2008},
 keywords = {Bandwidth,Bridges,Computer architecture,GSMP model,Manufacturing,Markov processes,Microelectronics,Monte Carlo methods,Monte Carlo simulation,Network-on-a-chip,Parameter estimation,Performance analysis,SoC communication architecture,System-on-a-chip,computer architecture,concurrent communication techniques,generalized semi Markov process model,hierarchical bus bridge communication architecture,hierarchical bus-bridge,integrated circuit design,memory bandwidth,performance estimation,performance parameters,processing element,queue length,queueing theory,system-on-chip,system-on-chip communication},
 pages = {155-158},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5393540},
 month = {12},
 publisher = {IEEE},
 id = {5e03f63f-88e0-3d7c-bbd1-3905037acec7},
 created = {2016-05-10T02:54:43.000Z},
 accessed = {2015-12-15},
 file_attached = {true},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2017-03-14T01:22:09.162Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Deshmukh2008a},
 short_title = {Microelectronics, 2008. ICM 2008. International Co},
 private_publication = {false},
 abstract = {The modern-day system-on-chip communication posses complex characteristics- (a) the communication times of individual transactions are difficult to predict, (b) concurrent communication techniques are employed to meet the performance of emerging applications, and (c) communication is hierarchical. Thus, performance of communication architecture plays major role in determining the performance of the system. An early and efficient performance estimation of communication architecture is essential in order to select appropriate communication architecture from the possible choices, within design time deadlines. In this paper, we propose an analytical technique for performance estimation of hierarchical bus bridge communication architecture, based on generalized semi Markov process (GSMP) model. Our modeling approach provides an early estimation of performance parameters viz. memory bandwidth, average queue length at memory and average waiting time seen by a processing element. The input parameters to the model are number of processing elements, the mean computation time of processing elements, and the first and second moments of communication time of processing elements. We validate efficacy of modeling approach by comparing the results against those obtained by Monte Carlo simulation for the underlying model.},
 bibtype = {inproceedings},
 author = {Deshmukh, Ulhas and Sahula, Vineet},
 doi = {10.1109/ICM.2008.5393540},
 booktitle = {Proceedings of the International Conference on Microelectronics, ICM}
}

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ICM 2008. International Co","private_publication":false,"abstract":"The modern-day system-on-chip communication posses complex characteristics- (a) the communication times of individual transactions are difficult to predict, (b) concurrent communication techniques are employed to meet the performance of emerging applications, and (c) communication is hierarchical. Thus, performance of communication architecture plays major role in determining the performance of the system. An early and efficient performance estimation of communication architecture is essential in order to select appropriate communication architecture from the possible choices, within design time deadlines. In this paper, we propose an analytical technique for performance estimation of hierarchical bus bridge communication architecture, based on generalized semi Markov process (GSMP) model. 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