@book{
 title = {VLSI Implementation of Tunable Band-Pass Notch IIR Filter for Localization of Hot spots in Proteins},
 type = {book},
 year = {2021},
 source = {Lecture Notes in Electrical Engineering},
 keywords = {IEEE-754 floating point standard,IIR digital filter,Protein hot spot detection,Proteomics},
 volume = {673},
 id = {21a7dfe9-449a-3d87-80a2-dbfa84fa2f0b},
 created = {2020-10-12T23:59:00.000Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2020-10-15T07:16:45.874Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2021, The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. A tunable band-pass notch (BPN) IIR digital filter (including zero phase filtering) is proposed by Ramachandran et al. in 2009 to detect the hot spot regions in proteins. The hot spots are the locations of amino acids at which proteins communicate with each other to achieve biological functions. In this paper, the tuning technique of above BPN filter is modified as per the characteristics frequency of protein functional group. The VLSI architecture of this tuned filter is developed and synthesized using Artix-7 family FPGA. The implemented architecture performance is compared with that obtained by MATLAB for FGF protein family. It is observed that the hardware provides approximately 51 times faster results than MATLAB run time.},
 bibtype = {book},
 author = {Pathak, V. and Nanda, S.J. and Joshi, A.M. and Sahu, S.S.},
 doi = {10.1007/978-981-15-5546-6_48}
}

© 2021, The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. A tunable band-pass notch (BPN) IIR digital filter (including zero phase filtering) is proposed by Ramachandran et al. in 2009 to detect the hot spot regions in proteins. The hot spots are the locations of amino acids at which proteins communicate with each other to achieve biological functions. In this paper, the tuning technique of above BPN filter is modified as per the characteristics frequency of protein functional group. The VLSI architecture of this tuned filter is developed and synthesized using Artix-7 family FPGA. The implemented architecture performance is compared with that obtained by MATLAB for FGF protein family. It is observed that the hardware provides approximately 51 times faster results than MATLAB run time.

@article{
 title = {Performance Investigation of Organic Thin Film Transistor on Varying Thickness of Semiconductor Material: An Experimentally Verified Simulation Study},
 type = {article},
 year = {2020},
 keywords = {mobility,organic thin-film transistor,semiconductor thickness},
 volume = {54},
 id = {08a3e3b0-6454-30a7-8965-9818821a99b2},
 created = {2020-11-07T23:59:00.000Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2020-11-11T21:06:54.606Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2020, Pleiades Publishing, Ltd. Abstract: Physics-based two-dimensional numerical simulations are performed to analyze the device characteristics of tri-isopropylsilylethynyl (TIPS)-pentacene organic thin-film transistor (OTFT) fabricated using drop-casting technique. Further, using simulation technique enabling calibration this paper also presents the systematic study of the impact of active layer (TIPS-pentacene) thickness on device characteristics. The extracted parameters such as electric field intensity, current density, current On/Off ratio, and mobility exhibit variation with scaling down in active layer thickness from 500 to 100 nm. The study also revealed that Off current and On/Off current ratio (IOn/IOff) is highly dependent on the thickness of the semiconductor layer. Furthermore, the highest value of IOn/IOff is obtained at 100-nm thickness of TIPS-pentacene, which can be used for various fast-switching applications in digital circuits. Simulated results are not only reasonably matching with experimental results but also provide insight on charge transportation at the semiconductor-dielectric interface and in the bulk of TIPS-pentacene layer.},
 bibtype = {article},
 author = {Jain, S.K. and Joshi, A.M. and Bharti, D.},
 doi = {10.1134/S106378262011010X},
 journal = {Semiconductors},
 number = {11}
}

© 2020, Pleiades Publishing, Ltd. Abstract: Physics-based two-dimensional numerical simulations are performed to analyze the device characteristics of tri-isopropylsilylethynyl (TIPS)-pentacene organic thin-film transistor (OTFT) fabricated using drop-casting technique. Further, using simulation technique enabling calibration this paper also presents the systematic study of the impact of active layer (TIPS-pentacene) thickness on device characteristics. The extracted parameters such as electric field intensity, current density, current On/Off ratio, and mobility exhibit variation with scaling down in active layer thickness from 500 to 100 nm. The study also revealed that Off current and On/Off current ratio (IOn/IOff) is highly dependent on the thickness of the semiconductor layer. Furthermore, the highest value of IOn/IOff is obtained at 100-nm thickness of TIPS-pentacene, which can be used for various fast-switching applications in digital circuits. Simulated results are not only reasonably matching with experimental results but also provide insight on charge transportation at the semiconductor-dielectric interface and in the bulk of TIPS-pentacene layer.

@article{
 title = {iGLU: An Intelligent Device for Accurate Noninvasive Blood Glucose-Level Monitoring in Smart Healthcare},
 type = {article},
 year = {2020},
 volume = {9},
 id = {7afd9627-432d-3e6a-88f0-54b9b13ec4b9},
 created = {2019-12-19T23:59:00.000Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2021-02-27T04:05:24.441Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {true},
 abstract = {© 2012 IEEE. In the case of diabetes, fingertip pricking for blood sample is inconvenient for glucose measurement. Invasive approaches like laboratory tests and one touch glucometers enhance the risk of blood related infections. To mitigate this important issue, this article introduces a novel Internet-of-Medical-Things (IoMT) enabled edge-device for precise, noninvasive blood glucose measurement. The device called Intelligent Glucose Meter (i.e., iGLU) is based on near-infrared (NIR) spectroscopy and a machine learning model of high accuracy. iGLU has been validated in a hospital and blood glucose values are stored in an IoMT platform for remote monitoring by endocrinologists.},
 bibtype = {article},
 author = {Jain, P. and Joshi, A.M. and Mohanty, S.P.},
 doi = {10.1109/MCE.2019.2940855},
 journal = {IEEE Consumer Electronics Magazine},
 number = {1}
}

© 2012 IEEE. In the case of diabetes, fingertip pricking for blood sample is inconvenient for glucose measurement. Invasive approaches like laboratory tests and one touch glucometers enhance the risk of blood related infections. To mitigate this important issue, this article introduces a novel Internet-of-Medical-Things (IoMT) enabled edge-device for precise, noninvasive blood glucose measurement. The device called Intelligent Glucose Meter (i.e., iGLU) is based on near-infrared (NIR) spectroscopy and a machine learning model of high accuracy. iGLU has been validated in a hospital and blood glucose values are stored in an IoMT platform for remote monitoring by endocrinologists.

@article{
 title = {VLSI Architecture of Block Matching Algorithms for Motion Estimation in High Efficiency Video Coding},
 type = {article},
 year = {2020},
 keywords = {High-efficiency video coding (HEVC),Mean absolute difference (MAD),Mean square error (MSE),Motion estimation,Quad-tree partitions,Sum of absolute difference (SAD)},
 volume = {112},
 id = {d0578c57-2231-389f-898b-6d31f292fbbd},
 created = {2020-02-01T23:59:00.000Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2021-03-04T23:49:58.173Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {true},
 abstract = {© 2020, Springer Science+Business Media, LLC, part of Springer Nature. High-efficiency video coding (HEVC) is a latest video coding standard and the motion estimation unit is the most important block. The work presents the different types of Matching Criteria for Block-Based Motion Estimation technique in HEVC standard. HEVC requires fast motion estimation algorithms to have better real time performance. The hardware implementation of motion estimation helps to achieve high speed though parallel processing. An improved block matching technique is designed with reduced blocks for HEVC. The proposed method has less execution time where only blocks having motion are compared for prediction computation. The searching time complexity is dependent on the number of blocks that are having motion. The searching time of frame having small motion can be reduced to 80–85% as compared to the traditional full search algorithm. In the paper, sum of absolute difference, mean square error and mean absolute difference are computed to find the best matching algorithm for HEVC. However, SAD has less computational complexity with compare to other matching criteria. The results suggest that proposed motion estimation algorithm has better performance with compare to similar previous work.},
 bibtype = {article},
 author = {Joshi, A.M. and Bramha, A.},
 doi = {10.1007/s11277-020-07081-z},
 journal = {Wireless Personal Communications},
 number = {2}
}

© 2020, Springer Science+Business Media, LLC, part of Springer Nature. High-efficiency video coding (HEVC) is a latest video coding standard and the motion estimation unit is the most important block. The work presents the different types of Matching Criteria for Block-Based Motion Estimation technique in HEVC standard. HEVC requires fast motion estimation algorithms to have better real time performance. The hardware implementation of motion estimation helps to achieve high speed though parallel processing. An improved block matching technique is designed with reduced blocks for HEVC. The proposed method has less execution time where only blocks having motion are compared for prediction computation. The searching time complexity is dependent on the number of blocks that are having motion. The searching time of frame having small motion can be reduced to 80–85% as compared to the traditional full search algorithm. In the paper, sum of absolute difference, mean square error and mean absolute difference are computed to find the best matching algorithm for HEVC. However, SAD has less computational complexity with compare to other matching criteria. The results suggest that proposed motion estimation algorithm has better performance with compare to similar previous work.

@article{
 title = {A precise non-invasive blood glucose measurement system using NIR spectroscopy and Huber’s regression model},
 type = {article},
 year = {2019},
 keywords = {Blood glucose measurement,NIR spectroscopy,Non-invasive system,Regression model,Statistical analysis},
 volume = {51},
 id = {9dd55191-17dd-31b7-ae3e-82a60cf54fb6},
 created = {2019-02-17T23:59:00.000Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2020-11-20T06:15:33.826Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2019, Springer Science+Business Media, LLC, part of Springer Nature.  Diabetes is one of the prominent diseases around the world. Presently, invasive techniques need a finger prick blood sample. A repetitively painful procedure that produces the chance of infection. To resolve this issue, non-invasive measurement approach is proposed. In this paper, an efficient NIR wave based optical detection system is proposed with optimized post-processing regression model. After real-time data analysis, it has been found that the coefficient of determination (R 2 ) is improved with the value of 0.9084 using proposed regression model. Mean absolute derivative is also increased with 3.87 mg/dl corresponding to predicted blood glucose concentration. Mean absolute relative difference has exceeded to 3.25%, and average error is improved with 3.77% using proposed regression model. Average accuaracy has been analyzed 94–95% for predicted blood glucose concentration.},
 bibtype = {article},
 author = {Jain, P. and Maddila, R. and Joshi, A.M.},
 doi = {10.1007/s11082-019-1766-3},
 journal = {Optical and Quantum Electronics},
 number = {2}
}

© 2019, Springer Science+Business Media, LLC, part of Springer Nature. Diabetes is one of the prominent diseases around the world. Presently, invasive techniques need a finger prick blood sample. A repetitively painful procedure that produces the chance of infection. To resolve this issue, non-invasive measurement approach is proposed. In this paper, an efficient NIR wave based optical detection system is proposed with optimized post-processing regression model. After real-time data analysis, it has been found that the coefficient of determination (R 2 ) is improved with the value of 0.9084 using proposed regression model. Mean absolute derivative is also increased with 3.87 mg/dl corresponding to predicted blood glucose concentration. Mean absolute relative difference has exceeded to 3.25%, and average error is improved with 3.77% using proposed regression model. Average accuaracy has been analyzed 94–95% for predicted blood glucose concentration.

@article{
 title = {Time Derivative Moments Based Feature Extraction Approach for Recognition of Upper Limb Motions Using EMG},
 type = {article},
 year = {2019},
 keywords = {Sensor applications,classification,electromyogram,feature extraction,pattern recognition (PR),time derivative moments (TDMs)},
 volume = {3},
 id = {9661cc2e-9a3e-3052-95b9-7f75bffa47a8},
 created = {2019-09-25T23:59:00.000Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2021-01-11T06:32:47.041Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2017 IEEE. Electromyography pattern recognition (EMG-PR) is extensively recognized in human-machine interactive applications such as prosthesis control and rehabilitation devices. Conventional time-domain (TD) features have been shown to produce a decent performance in upper limb movements' classification. However, performance limitation exists in terms of classification accuracy. Hence, a novel feature set extraction on time derivative moments is proposed to improve the performance of EMG-PR in upper limb motion classification. A standardized and benchmark data base NinaPro (subdatabase2) has been used for examination of the proposed feature set. A total of eight intact subjects (sub1-sub8) have been selected for eight grasping motion's EMG signal collection. For classification of features, three classification techniques (linear discriminant analysis (LDA), quadratic discriminant analysis (QDA), and support vector machine (SVM)) have been applied. The average improvisation with respect to the conventional TD features that was achieved for LDA, QDA, and SVM are 8.08%, 7.95%, and 6.41%, respectively.},
 bibtype = {article},
 author = {Pancholi, S. and Joshi, A.M.},
 doi = {10.1109/LSENS.2019.2906386},
 journal = {IEEE Sensors Letters},
 number = {4}
}

© 2017 IEEE. Electromyography pattern recognition (EMG-PR) is extensively recognized in human-machine interactive applications such as prosthesis control and rehabilitation devices. Conventional time-domain (TD) features have been shown to produce a decent performance in upper limb movements' classification. However, performance limitation exists in terms of classification accuracy. Hence, a novel feature set extraction on time derivative moments is proposed to improve the performance of EMG-PR in upper limb motion classification. A standardized and benchmark data base NinaPro (subdatabase2) has been used for examination of the proposed feature set. A total of eight intact subjects (sub1-sub8) have been selected for eight grasping motion's EMG signal collection. For classification of features, three classification techniques (linear discriminant analysis (LDA), quadratic discriminant analysis (QDA), and support vector machine (SVM)) have been applied. The average improvisation with respect to the conventional TD features that was achieved for LDA, QDA, and SVM are 8.08%, 7.95%, and 6.41%, respectively.

@inproceedings{
 title = {A Novel Time-Domain based Feature for EMG-PR Prosthetic and Rehabilitation Application},
 type = {inproceedings},
 year = {2019},
 keywords = {Amputees,Classification,EMG,Feature extraction,Prosthetics},
 id = {b36aa07a-92b8-32f4-9874-7cbb34529d16},
 created = {2020-01-22T23:59:00.000Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2021-03-04T04:20:01.168Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {true},
 abstract = {© 2019 IEEE. EMG signal is widely accepted in human-machine interaction applications, such as prosthesis control and rehabilitation devices. The existing feature extraction methods struggle to separate a variety of EMG based activities. In the proposed work, a novel feature defined as PAP (peak average power) has been proposed. This feature has been validated for NinaPro database which includes isometric, isotonic, grasp and finger force based upper limb motions. Further, the comparison of classification accuracy has been performed with well-known time domain based features. Significant classification performance enhancement has been observed in terms of accuracy with LDA and QDA techniques. In this experiment, three datasets have been created and analysis was performed. Consequently, the results show an average enhancement of 17.60%, 7.52% and 15.37% using the proposed approach for LDA in dataset-1, dataset-2, and dataset-3 respectively. Similarly for the same datasets, when QDA is used the proposed approach overrules the existing techniques with the average enhanced performance of 13.52%, 12.72%, and 15.40%. All the analysis has been done using MATLAB 2015a in the i7 core.},
 bibtype = {inproceedings},
 author = {Pancholi, S. and Jain, P. and Varghese, A. and Joshi, A.M.},
 doi = {10.1109/EMBC.2019.8857399},
 booktitle = {Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBS}
}

© 2019 IEEE. EMG signal is widely accepted in human-machine interaction applications, such as prosthesis control and rehabilitation devices. The existing feature extraction methods struggle to separate a variety of EMG based activities. In the proposed work, a novel feature defined as PAP (peak average power) has been proposed. This feature has been validated for NinaPro database which includes isometric, isotonic, grasp and finger force based upper limb motions. Further, the comparison of classification accuracy has been performed with well-known time domain based features. Significant classification performance enhancement has been observed in terms of accuracy with LDA and QDA techniques. In this experiment, three datasets have been created and analysis was performed. Consequently, the results show an average enhancement of 17.60%, 7.52% and 15.37% using the proposed approach for LDA in dataset-1, dataset-2, and dataset-3 respectively. Similarly for the same datasets, when QDA is used the proposed approach overrules the existing techniques with the average enhanced performance of 13.52%, 12.72%, and 15.40%. All the analysis has been done using MATLAB 2015a in the i7 core.

@article{
 title = {Portable EMG Data Acquisition Module for Upper Limb Prosthesis Application},
 type = {article},
 year = {2018},
 keywords = {Acquisition,LDA,QDA,SVM,classification,k-NN,prosthetic,sEMG},
 volume = {18},
 id = {979e07be-7bc9-366d-9279-790b19fee2d0},
 created = {2018-09-06T11:22:39.817Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:39.817Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2001-2012 IEEE. Electromyography (EMG) signals are gaining popularity to develop the prosthetics. In this paper, an efficient multi-channel EMG signal acquisition system has been proposed for upper limb prosthetic application. Various arm exercises have been performed to obtain EMG signals from five different arm muscles for the validation of developed hardware. The muscle's position has been selected by palpation method. Furthermore, the classification algorithms have been examined for seven different activities. Total 29 subjects have been chosen (25 intact and four Amputees) to acquire the EMG data by these activities. To classify the recorded EMG data set, nine time domain and seven frequency domain features have been extracted. A comparative analysis of different classifiers is presented for different muscle position of electrodes. The signal processing and classification algorithms have been processed in MATLAB 2016a. The accuracy of classification ranges for different classification algorithms from 57.69% to 99.92% for all subjects.},
 bibtype = {article},
 author = {Pancholi, S. and Joshi, A.M.},
 doi = {10.1109/JSEN.2018.2809458},
 journal = {IEEE Sensors Journal},
 number = {8}
}

© 2001-2012 IEEE. Electromyography (EMG) signals are gaining popularity to develop the prosthetics. In this paper, an efficient multi-channel EMG signal acquisition system has been proposed for upper limb prosthetic application. Various arm exercises have been performed to obtain EMG signals from five different arm muscles for the validation of developed hardware. The muscle's position has been selected by palpation method. Furthermore, the classification algorithms have been examined for seven different activities. Total 29 subjects have been chosen (25 intact and four Amputees) to acquire the EMG data by these activities. To classify the recorded EMG data set, nine time domain and seven frequency domain features have been extracted. A comparative analysis of different classifiers is presented for different muscle position of electrodes. The signal processing and classification algorithms have been processed in MATLAB 2016a. The accuracy of classification ranges for different classification algorithms from 57.69% to 99.92% for all subjects.

@article{
 title = {Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration},
 type = {article},
 year = {2018},
 keywords = {SDG-NMOS,SGS-PMOS,efficiency,full-wave bridge rectifier,leakage power,low power circuit},
 volume = {27},
 id = {89ee45cf-d5a4-34ca-902f-2e6daa710314},
 created = {2018-09-06T11:22:39.932Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:39.932Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2018 World Scientific Publishing Company. An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.},
 bibtype = {article},
 author = {Jain, P. and Joshi, A.},
 doi = {10.1142/S0218126618500925},
 journal = {Journal of Circuits, Systems and Computers},
 number = {6}
}

© 2018 World Scientific Publishing Company. An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.

@article{
 title = {Analyzing the impact of augmented transistor NMOS configuration on parameters of 4×1 multiplexer},
 type = {article},
 year = {2018},
 volume = {61},
 id = {62d4b544-5f39-3e95-8ca8-ab422ca693a3},
 created = {2018-09-06T11:22:40.020Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.020Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© Allerton Press, Inc., 2018 and P. Jain, A.M. Joshi, 2018, published in Izvestiya Vysshikh Uchebnykh Zavedenii. This paper represents the power and delay analysis of 4×1 multiplexer based on Augmented Transistor NMOS (AT-NMOS) configurations. Transistor’s total channel width at multiple levels are considered to determine the leakage power and delay performance at 45 nm technology. It is evaluated that the performance parameter is improved in the proposed design based on Augmented Shorted Gate-Source PMOS with NMOS (ASG-S PMOS-NMOS) configuration as compared to the 4×1 multiplexer based on Static Threshold AT-NMOS (ST-ATNMOS) configuration. Using this combination, we obtain the desired performance parameters of the design. In this paper, two types of 4×1 multiplexer models are introduced. It is shown that the leakage power can be largely reduced. The delay performance is also improved up to 5% at 1 V power supply under consideration of multiple levels of transistor’s channel width due to evaluation of different AT-NMOS configurations based 4×1 multiplexer models. The simulation work has been carried out using the Cadence Analog Virtuoso Spectre Simulator at 45 nm CMOS technology.},
 bibtype = {article},
 author = {Jain, P. and Joshi, A.M.},
 doi = {10.3103/S0735272718030044},
 journal = {Radioelectronics and Communications Systems},
 number = {3}
}

© Allerton Press, Inc., 2018 and P. Jain, A.M. Joshi, 2018, published in Izvestiya Vysshikh Uchebnykh Zavedenii. This paper represents the power and delay analysis of 4×1 multiplexer based on Augmented Transistor NMOS (AT-NMOS) configurations. Transistor’s total channel width at multiple levels are considered to determine the leakage power and delay performance at 45 nm technology. It is evaluated that the performance parameter is improved in the proposed design based on Augmented Shorted Gate-Source PMOS with NMOS (ASG-S PMOS-NMOS) configuration as compared to the 4×1 multiplexer based on Static Threshold AT-NMOS (ST-ATNMOS) configuration. Using this combination, we obtain the desired performance parameters of the design. In this paper, two types of 4×1 multiplexer models are introduced. It is shown that the leakage power can be largely reduced. The delay performance is also improved up to 5% at 1 V power supply under consideration of multiple levels of transistor’s channel width due to evaluation of different AT-NMOS configurations based 4×1 multiplexer models. The simulation work has been carried out using the Cadence Analog Virtuoso Spectre Simulator at 45 nm CMOS technology.

@article{
 title = {Carbon Nanotubes-Based Digitally Programmable Current Follower},
 type = {article},
 year = {2018},
 volume = {2018},
 id = {448df9db-ef6b-38e7-83ae-a3e1da704a97},
 created = {2018-09-06T11:22:40.176Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.176Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2018 S. K. Tripathi et al. The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10 nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET's parameters like chirality, pitch, and numbers of CNTs to perform the digital control operation. The circuit has minimum number of transistors and can control the output current digitally. A similar CMOS circuit with 32 nm CMOS parameters was also simulated and compared. The result shows that CMOS-based circuit requires 418.6 μW while CNFET-based circuit consumes 352.1 μW only. Further, the proposed circuit is used to realize a CNFET-based instrumentation amplifier with digitally programmable gain. The amplifier has a CMRR of 100 dB and ICMR equal to 0.806 V. The 3 dB bandwidth of the amplifier is 11.78 GHz which is suitable for the applications like navigation, radar instrumentation, and high-frequency signal amplification and conditioning.},
 bibtype = {article},
 author = {Tripathi, S.K. and Ansari, M.S. and Joshi, A.M.},
 doi = {10.1155/2018/1080817},
 journal = {VLSI Design}
}

© 2018 S. K. Tripathi et al. The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10 nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET's parameters like chirality, pitch, and numbers of CNTs to perform the digital control operation. The circuit has minimum number of transistors and can control the output current digitally. A similar CMOS circuit with 32 nm CMOS parameters was also simulated and compared. The result shows that CMOS-based circuit requires 418.6 μW while CNFET-based circuit consumes 352.1 μW only. Further, the proposed circuit is used to realize a CNFET-based instrumentation amplifier with digitally programmable gain. The amplifier has a CMRR of 100 dB and ICMR equal to 0.806 V. The 3 dB bandwidth of the amplifier is 11.78 GHz which is suitable for the applications like navigation, radar instrumentation, and high-frequency signal amplification and conditioning.

@book{
 title = {Detection of lung cancer with the fusion of computed tomography and positron emission tomography},
 type = {book},
 year = {2018},
 source = {Communications in Computer and Information Science},
 keywords = {CT scan,Feature extraction,Image fusion,K-NN,PET scan,SVM},
 volume = {828},
 id = {1c8b85a3-c2cd-3593-941a-2ceea66d72da},
 created = {2018-09-06T11:22:40.625Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.625Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© Springer Nature Singapore Pte Ltd. 2018. In this paper, a wavelet fusion based cancer detection methodology has been presented. The database includes 200 samples of CT scan, and 200 PET scans out of which 50% samples of each were normal. Decomposition of CT scan and PET scan images have been performed by using wavelet transform (using haar as a mother wavelet) of depth 5 and combining the details of decomposed images by using averaging fusion rule and inverse wavelet transform. Further, 200 fused images have been segmented by manual cropping method to extract the useful information or region of interests (ROIs). 17 features of each of 200 ROIs have been extracted using GLCM and feature vectors are prepared. Subsequently, the features have been classified using two classifiers support vector machine (SVM) and k-nearest neighbors algorithm (k-NN) using their different kernels. The accuracy of SVM vary from 95.5%–98% and accuracy of k-NN vary from 69.5%–95.5%. This indicates that fused images can be a more powerful tool to diagnose the lung cancer.},
 bibtype = {book},
 author = {Kaur, J. and Pancholi, S. and Joshi, A.M.},
 doi = {10.1007/978-981-10-8660-1_72}
}

© Springer Nature Singapore Pte Ltd. 2018. In this paper, a wavelet fusion based cancer detection methodology has been presented. The database includes 200 samples of CT scan, and 200 PET scans out of which 50% samples of each were normal. Decomposition of CT scan and PET scan images have been performed by using wavelet transform (using haar as a mother wavelet) of depth 5 and combining the details of decomposed images by using averaging fusion rule and inverse wavelet transform. Further, 200 fused images have been segmented by manual cropping method to extract the useful information or region of interests (ROIs). 17 features of each of 200 ROIs have been extracted using GLCM and feature vectors are prepared. Subsequently, the features have been classified using two classifiers support vector machine (SVM) and k-nearest neighbors algorithm (k-NN) using their different kernels. The accuracy of SVM vary from 95.5%–98% and accuracy of k-NN vary from 69.5%–95.5%. This indicates that fused images can be a more powerful tool to diagnose the lung cancer.

@inproceedings{
 title = {Fingerprint based biometric watermarking architecture using integer DCT},
 type = {inproceedings},
 year = {2017},
 keywords = {Blind Detection,Fast Fourier Transform,Integer DCT,Normalized Corelation,Real Time},
 id = {ae75deca-c85d-3ab8-a730-3c1c6cc9c4a1},
 created = {2018-09-06T11:22:39.818Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:39.818Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2016 IEEE. The recent growth in multimedia technologies has simplified the ways for the transmission, reproduction and manipulation of data. This has raised the concern over security issues of the data transmitted over the channel. Watermarking is the practice of embedding information into multimedia object for authentication and ownership identification. In present time, biometric identification has acquired much attention because of its distinctiveness and reliability. The fingerprints are believed to be one of the most popular biometric scheme. In the paper, the image watermarking algorithm is developed where fingerprint based biometric identification is inserted for authentication. The robustness and invisibility of the proposed method is confirmed on MATLAB platform. The payload of the proposed algorithm is higher than other existing scheme where watermark is embedded in each three color components of an RGB image. The algorithm is synthesized on Virtex 7 FPGA family using Xilinx ISE 14.7 to verify the hardware performance.},
 bibtype = {inproceedings},
 author = {Vashistha, A. and Joshi, A.M.},
 doi = {10.1109/TENCON.2016.7848556},
 booktitle = {IEEE Region 10 Annual International Conference, Proceedings/TENCON}
}

© 2016 IEEE. The recent growth in multimedia technologies has simplified the ways for the transmission, reproduction and manipulation of data. This has raised the concern over security issues of the data transmitted over the channel. Watermarking is the practice of embedding information into multimedia object for authentication and ownership identification. In present time, biometric identification has acquired much attention because of its distinctiveness and reliability. The fingerprints are believed to be one of the most popular biometric scheme. In the paper, the image watermarking algorithm is developed where fingerprint based biometric identification is inserted for authentication. The robustness and invisibility of the proposed method is confirmed on MATLAB platform. The payload of the proposed algorithm is higher than other existing scheme where watermark is embedded in each three color components of an RGB image. The algorithm is synthesized on Virtex 7 FPGA family using Xilinx ISE 14.7 to verify the hardware performance.

@article{
 title = {Low leakage and high CMRR CMOS differential amplifier for biomedical application},
 type = {article},
 year = {2017},
 keywords = {Differential amplifier,Efficiency,Gate cross-coupled NMOS transistors,Leakage power,Low power circuit,Pull-up and pull-down stacked transistors},
 volume = {93},
 id = {cb8c6a1e-516c-3ccf-81cd-29d901977f70},
 created = {2018-09-06T11:22:39.870Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:39.870Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2017, Springer Science+Business Media, LLC. A novel, competent, effortless, low leakage CMOS differential amplifier is explored with minimum deformation and proper power utilization. The proposed circuit can also represent a CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system. The proposed circuit is designed with the intention of supply the power either from VDDto VOUTor from VSSto VOUT. The proposed circuit has high CMRR. It means that the common mode voltage gain is minimum and differential mode voltage gain is high. The circuit is designed in such a way that the power supply couldn’t reach from VDDto VSSdirectly i.e. the driving power of the circuit couldn’t be short circuited. Due to this, the proposed circuit behaves like a perfect differential amplifier. Competent and speculative combinations of CMOS logic are utilized with cross coupled by Gate terminals of NMOS transistors to provide the better functionality of proposed differential amplifier circuit. The proposed circuit with unique combination of MOS has provided better performance parameters. Due to utilization of modified MOS structure with pull-up and pull-down stacked transistors, gain factor of differential amplifier is increased up to 5 dB with compare to other differential amplifier circuits and leakage power dissipation is reduced up to 49%. Proposed CMOS based differential amplifier is optimized at 45 nm CMOS technology. The simulations have been performed using cadence analog virtuoso spectre simulator. The experimental implementations have been done for analysis of leakage power and efficiency with better consistency through the proposed circuit.},
 bibtype = {article},
 author = {Jain, P. and Joshi, A.M.},
 doi = {10.1007/s10470-017-1027-y},
 journal = {Analog Integrated Circuits and Signal Processing},
 number = {1}
}

© 2017, Springer Science+Business Media, LLC. A novel, competent, effortless, low leakage CMOS differential amplifier is explored with minimum deformation and proper power utilization. The proposed circuit can also represent a CMOS analog front-end (AFE) circuit for portable biomedical signals acquisition system. The proposed circuit is designed with the intention of supply the power either from VDDto VOUTor from VSSto VOUT. The proposed circuit has high CMRR. It means that the common mode voltage gain is minimum and differential mode voltage gain is high. The circuit is designed in such a way that the power supply couldn’t reach from VDDto VSSdirectly i.e. the driving power of the circuit couldn’t be short circuited. Due to this, the proposed circuit behaves like a perfect differential amplifier. Competent and speculative combinations of CMOS logic are utilized with cross coupled by Gate terminals of NMOS transistors to provide the better functionality of proposed differential amplifier circuit. The proposed circuit with unique combination of MOS has provided better performance parameters. Due to utilization of modified MOS structure with pull-up and pull-down stacked transistors, gain factor of differential amplifier is increased up to 5 dB with compare to other differential amplifier circuits and leakage power dissipation is reduced up to 49%. Proposed CMOS based differential amplifier is optimized at 45 nm CMOS technology. The simulations have been performed using cadence analog virtuoso spectre simulator. The experimental implementations have been done for analysis of leakage power and efficiency with better consistency through the proposed circuit.

@book{
 title = {Low-noise tunable band-pass filter for ISM 2.4 GHZ bluetooth transceiver in ±0.7V 32 nm CNFET technology},
 type = {book},
 year = {2017},
 source = {Advances in Intelligent Systems and Computing},
 keywords = {CMOS Scaling,Carbon Nanotube Field Effect Transistor (CNFET),Current mode (CM),Dual-output inverting current conveyor (DOICC-II),Voltage mode (VM)},
 volume = {468},
 id = {b053af21-f6db-31ac-8126-4e5b04b88a8f},
 created = {2018-09-06T11:22:40.077Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.077Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© Springer Science+Business Media Singapore 2017. This paper presents a CNFET-based low-noise band-pass filter for application in 2.4 GHz Bluetooth transceivers. The proposed circuit exploits the ultrawide voltage and current bandwidths of CNFET-based analog building blocks as compared to their CMOS counterparts. Tuning of the center frequency is demonstrated via variation of a grounded resistor. SPICE simulations show that the CNFET-based building block consumes only 15% power as compared to its CMOS equivalent. Noise analysis and Monte Carlo analysis also demonstrate the high performance characteristics of the proposed circuit.},
 bibtype = {book},
 author = {Tripathi, S.K. and Ansari, M.S. and Joshi, A.M.},
 doi = {10.1007/978-981-10-1675-2_43}
}

© Springer Science+Business Media Singapore 2017. This paper presents a CNFET-based low-noise band-pass filter for application in 2.4 GHz Bluetooth transceivers. The proposed circuit exploits the ultrawide voltage and current bandwidths of CNFET-based analog building blocks as compared to their CMOS counterparts. Tuning of the center frequency is demonstrated via variation of a grounded resistor. SPICE simulations show that the CNFET-based building block consumes only 15% power as compared to its CMOS equivalent. Noise analysis and Monte Carlo analysis also demonstrate the high performance characteristics of the proposed circuit.

@inproceedings{
 title = {PWM waveform generation using rotary encoder on Spartan-3E starter kit},
 type = {inproceedings},
 year = {2017},
 keywords = {Duty Cycle,FPGA,PWM,Rotary encoder,Spartan 3E,Verilog,Xilinx},
 id = {0ef541de-99bc-3fac-8108-7ea3d17cc172},
 created = {2018-09-06T11:22:40.115Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.115Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2017 IEEE. A PWM waveform generator with variable duty cycle has been designed and implemented in this paper. The design has been simulated for different frequencies. The waveform is generated on Spartan 3E FPGA starter kit which has on board rotary encoder. The on board clock signal and rotary encoder generates the required PWM signal. The duty cycle of PWM is varied by rotating the encoder in clockwise and anticlockwise directions. Various frequencies of PWM signal is generated by pressing it up and down. The design has been proposed where duty cycle can be varied from 0 to 100%. The frequency of the on board clock signal i.e., 50 MHz and this has been varied to generate different frequencies. The output can be observed on DSO and CRO. The PWM is used in controlling inverters, electrical motors and many communication and control applications. The usage of FPGA provides the reconfigurable architecture and also provides flexibility as well as economically viable.},
 bibtype = {inproceedings},
 author = {Thakral, S. and Joshi, A.M. and Mehta, U.},
 doi = {10.1109/CIACT.2017.7977372},
 booktitle = {3rd IEEE International Conference on}
}

© 2017 IEEE. A PWM waveform generator with variable duty cycle has been designed and implemented in this paper. The design has been simulated for different frequencies. The waveform is generated on Spartan 3E FPGA starter kit which has on board rotary encoder. The on board clock signal and rotary encoder generates the required PWM signal. The duty cycle of PWM is varied by rotating the encoder in clockwise and anticlockwise directions. Various frequencies of PWM signal is generated by pressing it up and down. The design has been proposed where duty cycle can be varied from 0 to 100%. The frequency of the on board clock signal i.e., 50 MHz and this has been varied to generate different frequencies. The output can be observed on DSO and CRO. The PWM is used in controlling inverters, electrical motors and many communication and control applications. The usage of FPGA provides the reconfigurable architecture and also provides flexibility as well as economically viable.

@inproceedings{
 title = {FPGA implementation of advanced Encryption Standard algorithm},
 type = {inproceedings},
 year = {2017},
 keywords = {AES,Cipher text,Encryption,FPGA,Plain text,VHDL,Xilinx ISE},
 id = {820c7969-a242-3933-9f08-5e27a3537fac},
 created = {2018-09-06T11:22:40.218Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.218Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2016 IEEE. An AES is the most popular security algorithm and it is required to improve the performance of AES with increasing the demand of internet security. AES is a symmetric key algorithm in which only one key is requires for encryption and decryption process, key must be same. The AES implementation is possible for software and hardware but hardware implementation has better speed in comparison to software. In the proposed work, we implemented AES on FPGA as it provides reconfigurable hardware to verify the real-time implementation. The proposed design uses repetitive looping method with 128 bits block size and key size. AES implementation of our design is also compared with other designs to show the hardware utilization.},
 bibtype = {inproceedings},
 author = {Kouser, Z. and Singhal, M. and Joshi, A.M.},
 doi = {10.1109/ICRAIE.2016.7939594},
 booktitle = {2016 International Conference on Recent Advances and Innovations in Engineering, ICRAIE 2016}
}

© 2016 IEEE. An AES is the most popular security algorithm and it is required to improve the performance of AES with increasing the demand of internet security. AES is a symmetric key algorithm in which only one key is requires for encryption and decryption process, key must be same. The AES implementation is possible for software and hardware but hardware implementation has better speed in comparison to software. In the proposed work, we implemented AES on FPGA as it provides reconfigurable hardware to verify the real-time implementation. The proposed design uses repetitive looping method with 128 bits block size and key size. AES implementation of our design is also compared with other designs to show the hardware utilization.

@inproceedings{
 title = {Multiplier less high speed VLSI architecture for lifting based 1-D discrete wavelet transform},
 type = {inproceedings},
 year = {2017},
 keywords = {DCT,DWT,JPEG 2000,Lifting Scheme,MPEG 4,VLSI},
 id = {b14616aa-062a-3103-a7e3-5eef173026c3},
 created = {2018-09-06T11:22:40.388Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.388Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2016 IEEE. An efficient VLSI architecture of 1-D DWT based on lifting scheme is proposed for high speed applications. Multipliers are difficult to fabricate on chip and occupy more area. The paper presents multiplier-less DWT architecture. Since the lifting scheme suffers the longer critical path, irregular datapath, data dependencies. The critical path of proposed architecture is Ta which is the minimum possible critical path delay of DWT architecture. We have also used parallel flipping technique where addition and multiplication are processed in parallel manner. The proposed architecture archives 100% hardware utilization efficiency. The architecture is synthesized on Virtex-IV Xc4vfx20-12ff672 using VHDL.},
 bibtype = {inproceedings},
 author = {Dahiya, V. and Singhal, M. and Joshi, A.},
 doi = {10.1109/ICRAIE.2016.7939464},
 booktitle = {2016 International Conference on Recent Advances and Innovations in Engineering, ICRAIE 2016}
}

© 2016 IEEE. An efficient VLSI architecture of 1-D DWT based on lifting scheme is proposed for high speed applications. Multipliers are difficult to fabricate on chip and occupy more area. The paper presents multiplier-less DWT architecture. Since the lifting scheme suffers the longer critical path, irregular datapath, data dependencies. The critical path of proposed architecture is Ta which is the minimum possible critical path delay of DWT architecture. We have also used parallel flipping technique where addition and multiplication are processed in parallel manner. The proposed architecture archives 100% hardware utilization efficiency. The architecture is synthesized on Virtex-IV Xc4vfx20-12ff672 using VHDL.

@inproceedings{
 title = {VLSI architecture of integer DCT based watermarking with error correction capability},
 type = {inproceedings},
 year = {2017},
 keywords = {AC Prediction,Cross-correlation,Error Correction Code,Integer DCT,Robustness},
 volume = {2017-Decem},
 id = {ba8835de-754a-3886-b06d-ec0af93937ba},
 created = {2018-09-06T11:22:40.520Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.520Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2017 IEEE. The expansion in technology has explored the cost effective ways of replication & distribution for digital content with least effort. The digital watermark is a technique which can be useful to have an effective protection for authentication and proof of ownership. The proposed method uses Integer DCT with an error correction concept to improve the robustness of the watermarking system. The performance of proposed algorithm is validated on MATLAB in terms of Cross-Correlation with and without error correction code. The reliability of algorithm is also increased almost 10% to 20% with the help of error correction code. The payload of the proposed system is also higher compare to previous work. Experimental results have demonstrated the effectiveness against various attacks such as JPEG lossy compression, noise attacks and geometrical attacks. VLSI architecture of proposed algorithm is designed and hardware implementation is achieved to verify the real-time performance.},
 bibtype = {inproceedings},
 author = {Joshi, A.M. and Ansari, S. and Ravikumar, M.},
 doi = {10.1109/TENCON.2017.8228369},
 booktitle = {IEEE Region 10 Annual International Conference, Proceedings/TENCON}
}

© 2017 IEEE. The expansion in technology has explored the cost effective ways of replication & distribution for digital content with least effort. The digital watermark is a technique which can be useful to have an effective protection for authentication and proof of ownership. The proposed method uses Integer DCT with an error correction concept to improve the robustness of the watermarking system. The performance of proposed algorithm is validated on MATLAB in terms of Cross-Correlation with and without error correction code. The reliability of algorithm is also increased almost 10% to 20% with the help of error correction code. The payload of the proposed system is also higher compare to previous work. Experimental results have demonstrated the effectiveness against various attacks such as JPEG lossy compression, noise attacks and geometrical attacks. VLSI architecture of proposed algorithm is designed and hardware implementation is achieved to verify the real-time performance.

@inproceedings{
 title = {VLSI implementation of 3D integer DCT for video coding standards},
 type = {inproceedings},
 year = {2017},
 keywords = {quantization,redundancy,separable property,similarity factor,transformation},
 id = {f023cccb-ec37-35fb-87bd-52d1d427b982},
 created = {2018-09-06T11:22:40.524Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.524Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2016 IEEE. The paper presents a VLSI architecture of three dimensional discrete cosine transform (3D DCT) for video recent compression. By making use of the separability property of DCT, the 3D DCT is decomposed into 1D DCTs computed in each of the three dimensions. Each 1D DCT is carried out as an integer DCT using the butterfly structure. It is useful for reducing the computation time and also makes our structure fully modular. Finally, we have achieved compression by element multiplication of 3D DCT output with quantization matrix and then zigzag coding of the resultant output. The proposed method is implemented in Xilinx 14.7 software using Verilog and the results are verified by its MATLAB implementation. The result computes the mean square error and similarity factor for the original frames and reconstructed frames from the standard videos. The results show the comparable performance of proposed 3D DCT and helps in efficient implementation of video coding standard.},
 bibtype = {inproceedings},
 author = {Gupta, S. and Kalra, M. and Singhal, R. and Joshi, A.},
 doi = {10.1109/NGCT.2016.7877494},
 booktitle = {Proceedings on 2016 2nd International Conference on Next Generation Computing Technologies, NGCT 2016}
}

© 2016 IEEE. The paper presents a VLSI architecture of three dimensional discrete cosine transform (3D DCT) for video recent compression. By making use of the separability property of DCT, the 3D DCT is decomposed into 1D DCTs computed in each of the three dimensions. Each 1D DCT is carried out as an integer DCT using the butterfly structure. It is useful for reducing the computation time and also makes our structure fully modular. Finally, we have achieved compression by element multiplication of 3D DCT output with quantization matrix and then zigzag coding of the resultant output. The proposed method is implemented in Xilinx 14.7 software using Verilog and the results are verified by its MATLAB implementation. The result computes the mean square error and similarity factor for the original frames and reconstructed frames from the standard videos. The results show the comparable performance of proposed 3D DCT and helps in efficient implementation of video coding standard.

@inproceedings{
 title = {Hardware implementation of compressive sensing for image compression},
 type = {inproceedings},
 year = {2017},
 keywords = {Coherence,Compression,Independent&Identically Distributed (IID),Restricted Isometric Property (RIP),Sparsity},
 volume = {2017-Decem},
 id = {128c41ce-768d-3616-883e-c30e8695dd61},
 created = {2018-09-06T11:22:40.571Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.571Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2017 IEEE. Compressive sensing (CS) is one of the effective data compression methods where a small number of measurements of a sparse signal is required to have an exact recovery. In Compressive sensing technique, the data is acquired and compressed at the same time. CS concept allows capturing only fewer sparse and compressible signal which contains only useful information that helps to recover a proper signal. In this paper, image compression is performed with compressive sensing concept. The different basis matrices and sensing matrices are considered which satisfy the Restricted Isometric Property (RIP) and Independent and Identically Distributed (IID). The hardware implementation of CS is covered to have real-time compression for various image-based applications. The performance is observed regarding SNR, compression ratio, and correlation. The reconstruction algorithms are implemented on MATLAB platform. The obtained results show satisfactory performance for CS based image compression.},
 bibtype = {inproceedings},
 author = {Joshi, A.M. and Sahu, C. and Ravikumar, M. and Ansari, S.},
 doi = {10.1109/TENCON.2017.8228060},
 booktitle = {IEEE Region 10 Annual International Conference, Proceedings/TENCON}
}

© 2017 IEEE. Compressive sensing (CS) is one of the effective data compression methods where a small number of measurements of a sparse signal is required to have an exact recovery. In Compressive sensing technique, the data is acquired and compressed at the same time. CS concept allows capturing only fewer sparse and compressible signal which contains only useful information that helps to recover a proper signal. In this paper, image compression is performed with compressive sensing concept. The different basis matrices and sensing matrices are considered which satisfy the Restricted Isometric Property (RIP) and Independent and Identically Distributed (IID). The hardware implementation of CS is covered to have real-time compression for various image-based applications. The performance is observed regarding SNR, compression ratio, and correlation. The reconstruction algorithms are implemented on MATLAB platform. The obtained results show satisfactory performance for CS based image compression.

@inproceedings{
 title = {Memristor-based high performance third order quadrature oscillator},
 type = {inproceedings},
 year = {2017},
 keywords = {Memristor,Parametric oscillators,Quadrature oscillator},
 volume = {2017-Decem},
 id = {a1d56cff-20e3-307b-8624-ac61cf09239d},
 created = {2018-09-06T11:22:40.575Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.575Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2017 IEEE. This paper explores the possibility of utilizing the signature characteristics of a Memristor to obtain sustained low frequency oscillations from conventional oscillators. The case example considered in this work is a typical opamp-based third-order quadrature oscillator. It is demonstrated that the use of a Memristor instead of a resistor leads to improved oscillator characteristics. Specifically, it is shown that the frequency deviation as well as the THD is lower for Memristor-based oscillators in comparison to their resistor-based counterparts. This coupled with the smaller on-chip area offered by a Memristor would enable high-performance low frequency oscillators. PSPICE simulation results are included to support the claims.},
 bibtype = {inproceedings},
 author = {Sharma, V.K. and Ansari, M.S. and Joshi, A.M.},
 doi = {10.1109/TENCON.2017.8228367},
 booktitle = {IEEE Region 10 Annual International Conference, Proceedings/TENCON}
}

© 2017 IEEE. This paper explores the possibility of utilizing the signature characteristics of a Memristor to obtain sustained low frequency oscillations from conventional oscillators. The case example considered in this work is a typical opamp-based third-order quadrature oscillator. It is demonstrated that the use of a Memristor instead of a resistor leads to improved oscillator characteristics. Specifically, it is shown that the frequency deviation as well as the THD is lower for Memristor-based oscillators in comparison to their resistor-based counterparts. This coupled with the smaller on-chip area offered by a Memristor would enable high-performance low frequency oscillators. PSPICE simulation results are included to support the claims.

@inproceedings{
 title = {A Current-mode pH-Sensor Interface based on Carbon Nanotube Field Effect Transistor},
 type = {inproceedings},
 year = {2017},
 volume = {4},
 issue = {9},
 id = {bc9ec924-3749-3dd0-a390-17c27a2a4c32},
 created = {2018-09-06T11:22:40.645Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.645Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2017 Elsevier Ltd. The pH measurement has been widely used in application areas such as sensors, pharmacy, food-processing, biotechnology and laboratories etc. This paper attempts to explore an application of CNFET-based current conveyor (CC-II) for the design of a pH-sensor interface. The second generation current conveyor (CC-II) is a very versatile active building block and attained special interest for current-mode circuits. Additionally, proposed circuit utilizes only active element and passive component with low supply voltage of ±0.7V and consumes only 131.5μW of power. HSPICE simulations with 32 nm CNFET model have been performed to test the validity of the design.},
 bibtype = {inproceedings},
 author = {Tripathi, S.K. and Samar Ansari, M. and Joshi, A.M.},
 doi = {10.1016/j.matpr.2017.06.372},
 booktitle = {Materials Today: Proceedings}
}

© 2017 Elsevier Ltd. The pH measurement has been widely used in application areas such as sensors, pharmacy, food-processing, biotechnology and laboratories etc. This paper attempts to explore an application of CNFET-based current conveyor (CC-II) for the design of a pH-sensor interface. The second generation current conveyor (CC-II) is a very versatile active building block and attained special interest for current-mode circuits. Additionally, proposed circuit utilizes only active element and passive component with low supply voltage of ±0.7V and consumes only 131.5μW of power. HSPICE simulations with 32 nm CNFET model have been performed to test the validity of the design.

@book{
 title = {Combined DWT-DCT-based video watermarking algorithm using Arnold transform technique},
 type = {book},
 year = {2017},
 source = {Advances in Intelligent Systems and Computing},
 keywords = {Arnold transform,Blind detection,Copyright protection,Human visual system,Normalized correlation},
 volume = {468},
 id = {3d1368a9-1c96-3fba-80ee-cf8fc282fee5},
 created = {2018-09-06T11:22:40.686Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.686Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© Springer Science+Business Media Singapore 2017. The communication has become faster and easier through the Internet. The creation and delivery of various data (video, images, speech and audio) have grown by many fold. However, the processing of these data in the digital domain raises the issues like the content protection and providing the ownership of original content. Digital watermarking is a very useful technique which can overcome the shortcomings of current copyright laws of the digital data. Video is one of the most popular multimedia objects. Video watermarking is used to embed the ownership logo into the digital video content for the protection. The proposed algorithm uses energy compression property of DCT and multiresolution of DWT. The Arnold transformation technique is applied, which enhances the security level and also increases the robustness. Experiment results show that the proposed algorithm has the larger embedding capacity and the excellent robustness against all the attacks.},
 bibtype = {book},
 author = {Joshi, A.M. and Gupta, S. and Girdhar, M. and Agarwal, P. and Sarker, R.},
 doi = {10.1007/978-981-10-1675-2_45}
}

© Springer Science+Business Media Singapore 2017. The communication has become faster and easier through the Internet. The creation and delivery of various data (video, images, speech and audio) have grown by many fold. However, the processing of these data in the digital domain raises the issues like the content protection and providing the ownership of original content. Digital watermarking is a very useful technique which can overcome the shortcomings of current copyright laws of the digital data. Video is one of the most popular multimedia objects. Video watermarking is used to embed the ownership logo into the digital video content for the protection. The proposed algorithm uses energy compression property of DCT and multiresolution of DWT. The Arnold transformation technique is applied, which enhances the security level and also increases the robustness. Experiment results show that the proposed algorithm has the larger embedding capacity and the excellent robustness against all the attacks.

@inproceedings{
 title = {Design and implementation of a high speed digital FIR filter using unfolding},
 type = {inproceedings},
 year = {2017},
 keywords = {Carry Increment adder,FIR filter,Propagation delay,Unfolding,Vedic multiplier},
 id = {9a889f74-a5fa-3e63-8152-d48ff28668b6},
 created = {2018-09-06T11:22:40.705Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.705Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2016 IEEE. The paper presents the design and implementation of a high speed digital Finite Impulse Response (FIR) filter using unfolding transformation technique. FIR Filter has widespread applications in signal processing such as image processing, biomedical signal processing, high speed communication systems, noise elimination and many more. The speed of FIR filter can be improved with high speed vedic multiplier and with low propagation delay carry increment adder. In the proposed design, the FIR filter is unfolded by a factor 3 which results in scheduling the filter to a smaller iteration period and along with this throughput of the filter also increases. The propagation delay is reduced to almost three times in FIR filter by using faster adder, high speed multiplier and unfolding transformation technique. We have synthesized the proposed design on Xilinx ISE 14.7 with Virtex IV FPGA family. The obtained results also confirm the faster performance of the FIR filter.},
 bibtype = {inproceedings},
 author = {Thakral, S. and Goswami, D. and Sharma, R. and Prasanna, C.K. and Joshi, A.M.},
 doi = {10.1109/POWERI.2016.8077361},
 booktitle = {2016 IEEE 7th Power India International Conference, PIICON 2016}
}

© 2016 IEEE. The paper presents the design and implementation of a high speed digital Finite Impulse Response (FIR) filter using unfolding transformation technique. FIR Filter has widespread applications in signal processing such as image processing, biomedical signal processing, high speed communication systems, noise elimination and many more. The speed of FIR filter can be improved with high speed vedic multiplier and with low propagation delay carry increment adder. In the proposed design, the FIR filter is unfolded by a factor 3 which results in scheduling the filter to a smaller iteration period and along with this throughput of the filter also increases. The propagation delay is reduced to almost three times in FIR filter by using faster adder, high speed multiplier and unfolding transformation technique. We have synthesized the proposed design on Xilinx ISE 14.7 with Virtex IV FPGA family. The obtained results also confirm the faster performance of the FIR filter.

@inproceedings{
 title = {DWT-DCT based blind audio watermarking using Arnold scrambling and Cyclic codes},
 type = {inproceedings},
 year = {2016},
 keywords = {Arnold Transform,Copyright enforcement,Digital Media,Error Correcting Codes,Scrambling},
 id = {ba9e42ac-8549-32f5-9646-0e2e1115fca4},
 created = {2018-09-06T11:22:39.875Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:39.875Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2016 IEEE. Currently over the millions of digital audio files such as digital songs are copied illegally during file-sharing over the networks. It has resulted as the loss of revenue for music and broadcasting industries. The traditional protection schemes are no longer useful to protect copyright and ownership of multimedia objects. These challenges have prompted significant research in digital audio watermarking for protection and authentication. It helps to prevent forgery and impersonation of audio signal. In this paper, a novel audio watermarking based algorithm is proposed using Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT). Furthermore, the Arnold transform and error correction technique are utilized to improve the performance of proposed algorithm. The performance is measured using Bit Error Rate (BER), Peak Sound to Noise Ratio (PSNR) and Structural Similarity Index (SSIM) between the extracted watermark and original watermark. The experimental results show excellent resilience against typical signal processing attacks compared to the previous algorithm. The performance is improved in terms of BER for 0-3.9%, PSNR higher than 62-db and Structural Similarity Index (SSIM) from 0.99 to 1.},
 bibtype = {inproceedings},
 author = {Subir, undefined and Joshi, A.M.},
 doi = {10.1109/SPIN.2016.7566666},
 booktitle = {3rd International Conference on Signal Processing and Integrated Networks, SPIN 2016}
}

© 2016 IEEE. Currently over the millions of digital audio files such as digital songs are copied illegally during file-sharing over the networks. It has resulted as the loss of revenue for music and broadcasting industries. The traditional protection schemes are no longer useful to protect copyright and ownership of multimedia objects. These challenges have prompted significant research in digital audio watermarking for protection and authentication. It helps to prevent forgery and impersonation of audio signal. In this paper, a novel audio watermarking based algorithm is proposed using Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT). Furthermore, the Arnold transform and error correction technique are utilized to improve the performance of proposed algorithm. The performance is measured using Bit Error Rate (BER), Peak Sound to Noise Ratio (PSNR) and Structural Similarity Index (SSIM) between the extracted watermark and original watermark. The experimental results show excellent resilience against typical signal processing attacks compared to the previous algorithm. The performance is improved in terms of BER for 0-3.9%, PSNR higher than 62-db and Structural Similarity Index (SSIM) from 0.99 to 1.

@inproceedings{
 title = {Analysis of compressive sensing for non stationary music signal},
 type = {inproceedings},
 year = {2016},
 keywords = {Coherence,Compressive Sensing (CS),Independent & Identically Distributed (IID),Restricted Isometric Property (RIP),Sparsity},
 id = {0579b40c-c040-33db-b283-95d5f9035df6},
 created = {2018-09-06T11:22:39.988Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:39.988Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2016 IEEE. Compressive Sensing (CS) is the key method to reconstruct the signal with very few number of measurements as compared to conventional methods. According to the conventional Shannon-Nyquist sampling theory, the signal has to sample twice the bandwidth in order to have the proper reconstruction. It is required to store a large amount of data according to the conventional method. CS helps to resolve this issue with two important parameters such as the measurement matrix and the basis matrix. They should satisfy two properties which are Restricted Isometric Property (RIP) and Independent and Identically Distributed (IID). There are various reconstruction algorithms which are useful for the proper recovery of the signal after applying the CS technique. The work is carried out on different types of audible signals which are non-stationary in the nature. For the single tone audio signal, the value of SNR is quiet good. Whereas the SNR value of the music signal and the instrumental signal has been degraded because of the single tone frequency component. The value of RIP constant varies with the change in number of measurements.},
 bibtype = {inproceedings},
 author = {Joshi, A.M. and Upadhyaya, V.},
 doi = {10.1109/ICACCI.2016.7732203},
 booktitle = {2016 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2016}
}

© 2016 IEEE. Compressive Sensing (CS) is the key method to reconstruct the signal with very few number of measurements as compared to conventional methods. According to the conventional Shannon-Nyquist sampling theory, the signal has to sample twice the bandwidth in order to have the proper reconstruction. It is required to store a large amount of data according to the conventional method. CS helps to resolve this issue with two important parameters such as the measurement matrix and the basis matrix. They should satisfy two properties which are Restricted Isometric Property (RIP) and Independent and Identically Distributed (IID). There are various reconstruction algorithms which are useful for the proper recovery of the signal after applying the CS technique. The work is carried out on different types of audible signals which are non-stationary in the nature. For the single tone audio signal, the value of SNR is quiet good. Whereas the SNR value of the music signal and the instrumental signal has been degraded because of the single tone frequency component. The value of RIP constant varies with the change in number of measurements.

@article{
 title = {FPGA prototyping of video watermarking for ownership verification based on H.264/AVC},
 type = {article},
 year = {2016},
 keywords = {Bit plane slicing,Digital watermarking,FPGA,H.264,Integer DCT,Scene change detection},
 volume = {75},
 id = {bedbfe36-3ad6-3f0a-9c16-667a24b6e7da},
 created = {2018-09-06T11:22:40.148Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.148Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2015, Springer Science+Business Media New York. Digital video watermarking has drawn the attention towards authentication and proof of ownership. Uncompressed domain watermarking has flourished over the years and related algorithms have been implemented on the software platform. Software watermarking algorithms work offline where videos are captured through device and embedding algorithms run on a PC that is used to embed the watermark in the original video content. It doesn’t suffice real time requirements because of the delay that takes place between capturing and embedding the watermark. This delay involvement is more prone to attacks. Thus, it is essential to develop the system where the watermark gets embedded at the same time when video is being captured. In this paper, an efficient watermark embedding process has been portrayed which is suited to H.264/AVC standard. The proposed algorithm introduces the concept of scene change detection based on Integer Discrete Cosine Transform (Integer-DCT) using scene change detection. The different frames of a scene are embedded with different bit planes of the same watermark in order to improve the performance against temporal attacks. The algorithm is validated on the MATLAB platform and is prototyped on FPGA to show its feasibility for real-time application.},
 bibtype = {article},
 author = {Joshi, A.M. and Mishra, V. and Patrikar, R.M.},
 doi = {10.1007/s11042-014-2426-z},
 journal = {Multimedia Tools and Applications},
 number = {6}
}

© 2015, Springer Science+Business Media New York. Digital video watermarking has drawn the attention towards authentication and proof of ownership. Uncompressed domain watermarking has flourished over the years and related algorithms have been implemented on the software platform. Software watermarking algorithms work offline where videos are captured through device and embedding algorithms run on a PC that is used to embed the watermark in the original video content. It doesn’t suffice real time requirements because of the delay that takes place between capturing and embedding the watermark. This delay involvement is more prone to attacks. Thus, it is essential to develop the system where the watermark gets embedded at the same time when video is being captured. In this paper, an efficient watermark embedding process has been portrayed which is suited to H.264/AVC standard. The proposed algorithm introduces the concept of scene change detection based on Integer Discrete Cosine Transform (Integer-DCT) using scene change detection. The different frames of a scene are embedded with different bit planes of the same watermark in order to improve the performance against temporal attacks. The algorithm is validated on the MATLAB platform and is prototyped on FPGA to show its feasibility for real-time application.

@inproceedings{
 title = {New power gated SRAM cell in 90nm CMOS technology with low leakage current and high data stability for sleep mode},
 type = {inproceedings},
 year = {2015},
 keywords = {Data stability,Leakage current,Power gating,Power reduction,Static Noise Margin},
 id = {96e47ff9-165b-3263-8659-f670af47dfa5},
 created = {2018-09-06T11:22:39.961Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:39.961Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2014 IEEE. Static Random Access Memory (SRAM) is the most popular circuit which is used in all processors and occupies the considerable area of the chip. The total power consumption of circuit is largely dependent on power dissipated by memory. There were several efforts for reduction in power consumption such as Power Gated SRAM circuits and increasing virtual ground voltage. The previous techniques were capable to have either high data stability or low leakage current. The paper presents an implementation of a New Power Gated technique which is used to have low leakage current for sleep mode. It also helps to enhance the Static Noise Margin (SNM). Data stability, leakage current, write margin and power consumption are calculated and compared among conventional 6T SRAM, Old Power Gated SRAM and New Power Gated SRAM circuits. All the results are implemented in 90nm CMOS technology using HSPICE tools.},
 bibtype = {inproceedings},
 author = {Meena, N. and Joshi, A.M.},
 doi = {10.1109/ICCIC.2014.7238333},
 booktitle = {2014 IEEE International Conference on Computational Intelligence and Computing Research, IEEE ICCIC 2014}
}

© 2014 IEEE. Static Random Access Memory (SRAM) is the most popular circuit which is used in all processors and occupies the considerable area of the chip. The total power consumption of circuit is largely dependent on power dissipated by memory. There were several efforts for reduction in power consumption such as Power Gated SRAM circuits and increasing virtual ground voltage. The previous techniques were capable to have either high data stability or low leakage current. The paper presents an implementation of a New Power Gated technique which is used to have low leakage current for sleep mode. It also helps to enhance the Static Noise Margin (SNM). Data stability, leakage current, write margin and power consumption are calculated and compared among conventional 6T SRAM, Old Power Gated SRAM and New Power Gated SRAM circuits. All the results are implemented in 90nm CMOS technology using HSPICE tools.

@inproceedings{
 title = {Comparative analysis of basis & measurement matrices for non-speech audio signal using compressive sensing},
 type = {inproceedings},
 year = {2015},
 id = {b8de9c19-29fc-3f8a-96b0-91eb115a70f6},
 created = {2018-09-06T11:22:40.225Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.225Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2014 IEEE. Compressive sensing is the concept of reducing sampling rate of a signal. It reduces the required number of samples for signal representation at much lower rate than Nyquist's rate. High speed applications require high sampling rate that overburdens the role of ADC in signal processing. So in such cases compressive sensing plays a major role for improvement of performance. The work is based on music signal (non-speech audio signal) by iterating on various combinations of the sensing matrix and basis matrix to find the best suited for desired application. One of the sensing matrix provides the best incoherence and Restricted Isometric Property (RIP) for a particular basis matrix. This combination gives an optimum value of Signal to Noise Ratio (SNR). In order to have faithful recovery, it is necessary to fulfill certain properties that require a perfect combination of basis matrix and sensing matrix. This has also analyzed in the paper.},
 bibtype = {inproceedings},
 author = {Bhadoria, B.S. and Shukla, U. and Joshi, A.M.},
 doi = {10.1109/ICCIC.2014.7238453},
 booktitle = {2014 IEEE International Conference on Computational Intelligence and Computing Research, IEEE ICCIC 2014}
}

© 2014 IEEE. Compressive sensing is the concept of reducing sampling rate of a signal. It reduces the required number of samples for signal representation at much lower rate than Nyquist's rate. High speed applications require high sampling rate that overburdens the role of ADC in signal processing. So in such cases compressive sensing plays a major role for improvement of performance. The work is based on music signal (non-speech audio signal) by iterating on various combinations of the sensing matrix and basis matrix to find the best suited for desired application. One of the sensing matrix provides the best incoherence and Restricted Isometric Property (RIP) for a particular basis matrix. This combination gives an optimum value of Signal to Noise Ratio (SNR). In order to have faithful recovery, it is necessary to fulfill certain properties that require a perfect combination of basis matrix and sensing matrix. This has also analyzed in the paper.

@article{
 title = {Real time implementation of integer DCT based video watermarking architecture},
 type = {article},
 year = {2015},
 keywords = {H.264,Integer DCT,Parallel processing,Real time watermarking,Recursive architecture},
 volume = {12},
 id = {077eb3e7-736c-35e0-a4ed-69c622596472},
 created = {2018-09-06T11:22:40.276Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.276Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2015, Zarka Private Univ. All rights reserved. With the recent development in multimedia communication network, data integrity and security of original content is the area of concern. Video is the one of the most popular object which is being shared easily throughout the media. Video watermarking is the current state of research to resolve the video ownership and authenticity related issues. There is a substantial amount of development in software based video watermarking from last few years. The prior works mainly focused on video watermarking that targeted for raw video where the watermark is embedded on the uncompressed video. At the present video capturing devices produce their output in one of the video compression standard. Software watermarking introduces a measurable quantity of delay between video capturing and watermark embedding process. Thus, software watermarking is not one of the ideal choices for real time watermark embedding. In the paper, a novel invisible and robust integer Discrete Cosine Transform (DCT) based video watermarking has been proposed. The proposed video watermarking is developed for real time watermark embedding and can easily be adapted as primary part of H.264 encoder. The proposed algorithm has an essential part in form of integer DCT. Integer DCT is implemented with two different approaches, one is with fully pipeline architecture and the other is recursive architecture, for better speed and area optimization. The robustness of the algorithm has been improved against some video attacks with introducing the concept of scene change detection.},
 bibtype = {article},
 author = {Joshi, A. and Mishra, V. and Patrikar, R.},
 journal = {International Arab Journal of Information Technology},
 number = {6A}
}

© 2015, Zarka Private Univ. All rights reserved. With the recent development in multimedia communication network, data integrity and security of original content is the area of concern. Video is the one of the most popular object which is being shared easily throughout the media. Video watermarking is the current state of research to resolve the video ownership and authenticity related issues. There is a substantial amount of development in software based video watermarking from last few years. The prior works mainly focused on video watermarking that targeted for raw video where the watermark is embedded on the uncompressed video. At the present video capturing devices produce their output in one of the video compression standard. Software watermarking introduces a measurable quantity of delay between video capturing and watermark embedding process. Thus, software watermarking is not one of the ideal choices for real time watermark embedding. In the paper, a novel invisible and robust integer Discrete Cosine Transform (DCT) based video watermarking has been proposed. The proposed video watermarking is developed for real time watermark embedding and can easily be adapted as primary part of H.264 encoder. The proposed algorithm has an essential part in form of integer DCT. Integer DCT is implemented with two different approaches, one is with fully pipeline architecture and the other is recursive architecture, for better speed and area optimization. The robustness of the algorithm has been improved against some video attacks with introducing the concept of scene change detection.

@inproceedings{
 title = {Low complexity hardware implementation of quantization and CAVLC for H.264 encoder},
 type = {inproceedings},
 year = {2015},
 keywords = {Context Adaption,High Defination,Optimization,Real Time Performance,Scaling},
 id = {4c83f464-34fa-3ba0-bf98-6e0a5b583bef},
 created = {2018-09-06T11:22:40.333Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.333Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2014 IEEE. H.264 is the advance video coding standard for the compression and distribution of a video content. It has larger complexity in order to satisfy the demand of high quality video at low bit rate. Moreover, it requires the effective implementation of all its internal blocks. In the paper, we focuses on the implementation of two important blocks for H.264 encoder. We propose low complexity design of quantization and Context Adaptive Variable Length Coding (CAVLC). The quantization process is responsible for scaling down the value of transform coefficients. CAVLC is useful for a bit stream generation and it is adopted from the concept of modified Variable Length Coding (VLC) technique. The efficient architectures are designed for quantization and CAVLC blocks to have parallel and pipeline data processing. They are implemented on Virtex 4 XC4VLX40 FPGA family using VHDL. The synthesized results are obtained with Xilinx ISE 14.2 and resource, device utilization and timing analysis are reported. The results are compared with related work that shows the better real time performance of both blocks.},
 bibtype = {inproceedings},
 author = {Joshi, A.M. and Mishra, V. and Patrikar, R.M.},
 doi = {10.1109/ICCIC.2014.7238382},
 booktitle = {2014 IEEE International Conference on Computational Intelligence and Computing Research, IEEE ICCIC 2014}
}

© 2014 IEEE. H.264 is the advance video coding standard for the compression and distribution of a video content. It has larger complexity in order to satisfy the demand of high quality video at low bit rate. Moreover, it requires the effective implementation of all its internal blocks. In the paper, we focuses on the implementation of two important blocks for H.264 encoder. We propose low complexity design of quantization and Context Adaptive Variable Length Coding (CAVLC). The quantization process is responsible for scaling down the value of transform coefficients. CAVLC is useful for a bit stream generation and it is adopted from the concept of modified Variable Length Coding (VLC) technique. The efficient architectures are designed for quantization and CAVLC blocks to have parallel and pipeline data processing. They are implemented on Virtex 4 XC4VLX40 FPGA family using VHDL. The synthesized results are obtained with Xilinx ISE 14.2 and resource, device utilization and timing analysis are reported. The results are compared with related work that shows the better real time performance of both blocks.

@inproceedings{
 title = {An efficient DCT based image watermarking scheme for protecting distribution rights},
 type = {inproceedings},
 year = {2015},
 keywords = {Blind retrieval,Digital Rights Management,Invisibility,Robustness},
 id = {96b5736a-a6b8-3214-baa4-012b5a80b239},
 created = {2018-09-06T11:22:40.337Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.337Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2015 IEEE. The chances of copiright violation and piracy have been increased due to growth of networking and technology. Digital watermark is useful to verify the integrity of the content and for authenticity of an owner. The digital watermark must be robust against various attacks in order to protect the copiright information which is embedded in the original content. The proposed algorithm is useful for protecting the distribution rights of digital images. Watermark is embedded in the DCT coefficients of the host image and the watermark is pseudo randomly spread over the entire image using Linear Feedback Shift Register (LFSR). The algorithm shows improvement over existing algorithms in terms of Normalized Correlation (NC), Tamper Assessment Function (TAF) and Peak Signal to Noise ratio (PSNR). The proposed algorithm outperforms the related previous work with better results.},
 bibtype = {inproceedings},
 author = {Gupta, G. and Joshi, A.M. and Sharma, K.},
 doi = {10.1109/IC3.2015.7346655},
 booktitle = {2015 8th International Conference on Contemporary Computing, IC3 2015}
}

© 2015 IEEE. The chances of copiright violation and piracy have been increased due to growth of networking and technology. Digital watermark is useful to verify the integrity of the content and for authenticity of an owner. The digital watermark must be robust against various attacks in order to protect the copiright information which is embedded in the original content. The proposed algorithm is useful for protecting the distribution rights of digital images. Watermark is embedded in the DCT coefficients of the host image and the watermark is pseudo randomly spread over the entire image using Linear Feedback Shift Register (LFSR). The algorithm shows improvement over existing algorithms in terms of Normalized Correlation (NC), Tamper Assessment Function (TAF) and Peak Signal to Noise ratio (PSNR). The proposed algorithm outperforms the related previous work with better results.

@article{
 title = {Design of real-time video watermarking based on Integer DCT for H.264 encoder},
 type = {article},
 year = {2015},
 keywords = {H.264,Histogram difference,Integer DCT,Scene change detection,Watermarking},
 volume = {102},
 id = {d53e7c6c-1c3d-3f67-add4-e2ba48982468},
 created = {2018-09-06T11:22:40.398Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.398Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {© 2014 Taylor  &  Francis. With the advent of technology, video has become a prominent entity that is shared over networks. With easy availability of various editing tools, data integrity and ownership issues have caused great concern worldwide. Video watermarking is an evolving field that may be used to address such issues. Till date, most of the algorithms have been developed for uncompressed domain watermarking and implemented on software platforms. They provide flexibility and simplicity, but at the same time, they are not suited for real-time applications. They work offline where videos are captured and then watermark is embedded in the video. In the present work, a hardware-based implementation of video watermarking is proposed that overcomes the limitation of software watermarking methods and can be readily adapted to the H.264 standard. This paper focuses on an invisible and robust video watermarking scheme, which can be easily implemented as an integral part of the standard H.264 encoder. The proposed watermarking algorithm involves Integer DCT-based watermark embedding method, wherein Integer DCT is calculated with a fully parallel approach resulting in better speed. The proposed video watermarking is designed with pipelining and parallel architecture for real-time implementation. Here, scene change detection technique is used to improve the performance. Different planes of the watermark are embedded in different frames of a particular scene in order to achieve robustness against various temporal attacks.},
 bibtype = {article},
 author = {Joshi, A.M. and Mishra, V. and Patrikar, R.M.},
 doi = {10.1080/00207217.2014.954634},
 journal = {International Journal of Electronics},
 number = {1}
}

© 2014 Taylor & Francis. With the advent of technology, video has become a prominent entity that is shared over networks. With easy availability of various editing tools, data integrity and ownership issues have caused great concern worldwide. Video watermarking is an evolving field that may be used to address such issues. Till date, most of the algorithms have been developed for uncompressed domain watermarking and implemented on software platforms. They provide flexibility and simplicity, but at the same time, they are not suited for real-time applications. They work offline where videos are captured and then watermark is embedded in the video. In the present work, a hardware-based implementation of video watermarking is proposed that overcomes the limitation of software watermarking methods and can be readily adapted to the H.264 standard. This paper focuses on an invisible and robust video watermarking scheme, which can be easily implemented as an integral part of the standard H.264 encoder. The proposed watermarking algorithm involves Integer DCT-based watermark embedding method, wherein Integer DCT is calculated with a fully parallel approach resulting in better speed. The proposed video watermarking is designed with pipelining and parallel architecture for real-time implementation. Here, scene change detection technique is used to improve the performance. Different planes of the watermark are embedded in different frames of a particular scene in order to achieve robustness against various temporal attacks.

@inproceedings{
 title = {A survey on recent advances in speech compressive sensing},
 type = {inproceedings},
 year = {2013},
 keywords = {Compressive sensing,data acquisition,recovery algorithm,sparsity,speech synthesis},
 id = {c7bddaef-189b-321b-a351-c21d743e1d01},
 created = {2018-09-06T11:22:40.476Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.476Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {Compressive sensing (CS) is one of the upcoming fields which have paved its way for different approaches towards the signal acquisition and processing systems. In past years, many fields of application have emerged, where speech is one of the most popular one. Due to stochastic nature of speech signal, we are still in search for a proper sparse representation of the signal, so that we could easily incorporate CS and thereby reduce the increasing burden on the ADC. In this paper, we discuss some of the works which have been carried out towards the sparse representation of the speech signals. The idea is to concatenate them on a common platform by exploiting the signal and its basis matrices. Each of the approaches has its own pros and corns for the sparse representation. © 2013 IEEE.},
 bibtype = {inproceedings},
 author = {Shukla, U.P. and Patel, N.B. and Joshi, A.M.},
 doi = {10.1109/iMac4s.2013.6526422},
 booktitle = {Proceedings - 2013 IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, iMac4s 2013}
}

Compressive sensing (CS) is one of the upcoming fields which have paved its way for different approaches towards the signal acquisition and processing systems. In past years, many fields of application have emerged, where speech is one of the most popular one. Due to stochastic nature of speech signal, we are still in search for a proper sparse representation of the signal, so that we could easily incorporate CS and thereby reduce the increasing burden on the ADC. In this paper, we discuss some of the works which have been carried out towards the sparse representation of the speech signals. The idea is to concatenate them on a common platform by exploiting the signal and its basis matrices. Each of the approaches has its own pros and corns for the sparse representation. © 2013 IEEE.

@inproceedings{
 title = {Design of low complexity video watermarking algorithm based on integer DCT},
 type = {inproceedings},
 year = {2012},
 keywords = {H.264,Histogram,Integer DCT,Robust,Watermarking},
 id = {8474c7dd-c1ae-314c-af4b-adb408858900},
 created = {2018-09-06T11:22:40.456Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.456Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {Watermarking is the process of hiding a predefined pattern or logo into multimedia like image, audio or video in a way that quality and imperceptibility of media is preserved. Predefined pattern or logo represents the identification of the author. In recent years, rapid growth in digital multimedia has been noticed. Digital videos are widely exchanged on the internet with great ease and monetary involment, thus the security of video is main concern in todays digital world. H.264 is currently proposed standard for low bit rate video applications. H.264 provides high quality than any other previous standards with implementation of integer transformation. The proposed algorithm has been implemented for video with Integer based Discrete Cosine Transform for higher speed and low complexity. The blind algorithm based on scene change detection scheme has been implemented and verified to check robustness against temporal as well as some standard attacks. The algorithm has been implemented on VIRTEX-4 FPGA board and results evident the fact of the watermarking algorithm being efficient in terms of low complexity and high speed. © 2012 IEEE.},
 bibtype = {inproceedings},
 author = {Joshi, A.M. and Patrikar, R.M. and Mishra, V.},
 doi = {10.1109/SPCOM.2012.6290046},
 booktitle = {2012 International Conference on Signal Processing and Communications, SPCOM 2012}
}

Watermarking is the process of hiding a predefined pattern or logo into multimedia like image, audio or video in a way that quality and imperceptibility of media is preserved. Predefined pattern or logo represents the identification of the author. In recent years, rapid growth in digital multimedia has been noticed. Digital videos are widely exchanged on the internet with great ease and monetary involment, thus the security of video is main concern in todays digital world. H.264 is currently proposed standard for low bit rate video applications. H.264 provides high quality than any other previous standards with implementation of integer transformation. The proposed algorithm has been implemented for video with Integer based Discrete Cosine Transform for higher speed and low complexity. The blind algorithm based on scene change detection scheme has been implemented and verified to check robustness against temporal as well as some standard attacks. The algorithm has been implemented on VIRTEX-4 FPGA board and results evident the fact of the watermarking algorithm being efficient in terms of low complexity and high speed. © 2012 IEEE.

@inproceedings{
 title = {Design and implementation of real-time image watermarking},
 type = {inproceedings},
 year = {2011},
 keywords = {bit plane slicing,digital right management,digital watermarking,discrete wavelet transform,multimedia},
 id = {e546e802-6bc0-3f77-8d17-913c1574a22e},
 created = {2018-09-06T11:22:40.282Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.282Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {The digital watermarking is a multimedia technology for information hiding which provides the authentication and copyright protection. The digital images are easily exchanged through internet and threaten to some malicious attacks. Wavelet based frequency domain watermarking provides the robustness against different attacks. Bit plane slicing scheme of spatial domain watermarking provides lesser computational complexity suitable for real time implementation. We combine advantages of the both the domains for the proposed algorithm. We have developed algorithm for robust and invisible application where we used non blind detection scheme. This approach is also implemented on FPGA. Several software implementations of the watermarking algorithms are available, but very few attempts have been made for hardware implementations. Software based watermarking schemes are more prone to offline attacks due to the delay between image captured and embedding the watermark. Hardware based watermarking provides real time embedding process where watermark is embedded at the same time when image is captured. This is very much useful in applications like real-time broad casting, video authentication and secure camera system for courtroom evidence. The goal of hardware implementation is to achieve low-power, high-performance, real-time, reliable and secure watermarking systems using FPGA. © 2011 IEEE.},
 bibtype = {inproceedings},
 author = {Joshi, A.M. and Darji, A. and Mishra, V.},
 doi = {10.1109/ICSPCC.2011.6061762},
 booktitle = {2011 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2011}
}

The digital watermarking is a multimedia technology for information hiding which provides the authentication and copyright protection. The digital images are easily exchanged through internet and threaten to some malicious attacks. Wavelet based frequency domain watermarking provides the robustness against different attacks. Bit plane slicing scheme of spatial domain watermarking provides lesser computational complexity suitable for real time implementation. We combine advantages of the both the domains for the proposed algorithm. We have developed algorithm for robust and invisible application where we used non blind detection scheme. This approach is also implemented on FPGA. Several software implementations of the watermarking algorithms are available, but very few attempts have been made for hardware implementations. Software based watermarking schemes are more prone to offline attacks due to the delay between image captured and embedding the watermark. Hardware based watermarking provides real time embedding process where watermark is embedded at the same time when image is captured. This is very much useful in applications like real-time broad casting, video authentication and secure camera system for courtroom evidence. The goal of hardware implementation is to achieve low-power, high-performance, real-time, reliable and secure watermarking systems using FPGA. © 2011 IEEE.

@inproceedings{
 title = {Efficient dual domain watermarking scheme for secure images},
 type = {inproceedings},
 year = {2009},
 keywords = {Digital watermark,Discrete cosine transform,Discrete wavelet transform,Least significeny bit,Ownership},
 id = {affd570e-8ef4-3e01-9595-3465c05a86fc},
 created = {2018-09-06T11:22:40.062Z},
 file_attached = {false},
 profile_id = {11ae403c-c558-3358-87f9-dadc957bb57d},
 last_modified = {2018-09-06T11:22:40.062Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {Day to day growth of multimedia technology draws great attention for security. Digital images can be easily altered with software. This problems demand copyright protection and ownership verification. Digital watermarking is proposed as one of the ways to accomplish this, in which Digital watermarks are generally embedded into digital images in a manner that make the watermark invisible to a human observer as such watermarks do not cause degradation in the visual quality, or in the usefulness of the images. Digital watermarking is a technique to insert owner's identity into images for authentication. Digital watermarking has emerged as a new area of research for the Intellectual Property (IP) protection of images. Spatial domain watermarking has advantage of less computational cost. Frequency domain watermarking provides more robustness. The proposed algorithm has been developed to take advantage of both spatial as well as frequency domain properties. © 2009 IEEE.},
 bibtype = {inproceedings},
 author = {Joshi, A.M. and Darji, A.},
 doi = {10.1109/ARTCom.2009.215},
 booktitle = {ARTCom 2009 - International Conference on Advances in Recent Technologies in Communication and Computing}
}

Day to day growth of multimedia technology draws great attention for security. Digital images can be easily altered with software. This problems demand copyright protection and ownership verification. Digital watermarking is proposed as one of the ways to accomplish this, in which Digital watermarks are generally embedded into digital images in a manner that make the watermark invisible to a human observer as such watermarks do not cause degradation in the visual quality, or in the usefulness of the images. Digital watermarking is a technique to insert owner's identity into images for authentication. Digital watermarking has emerged as a new area of research for the Intellectual Property (IP) protection of images. Spatial domain watermarking has advantage of less computational cost. Frequency domain watermarking provides more robustness. The proposed algorithm has been developed to take advantage of both spatial as well as frequency domain properties. © 2009 IEEE.